33FJ128GP708 datasheet(20/90 Pages) MICROCHIP

20 / 90 page

dsPIC33F

DS70155C-page 18

Preliminary

5.1

Interrupt Priority

Each interrupt source can be user-assigned to one of

8 priority levels, 0 through 7. Levels 7 and 1 represent

the

highest

and

lowest

maskable

priorities,

respectively. A priority level of 0 disables the interrupt.

Since more than one interrupt request source may be

assigned to a user-specified priority level, a means is

provided to assign priority within a given level. This

method is called “Natural Order Priority”.

The Natural Order Priority of an interrupt is numerically

identical to its vector number. The Natural Order

Priority scheme has 0 as the highest priority and 74 as

the lowest priority.

The ability for the user to assign every interrupt to one

of eight priority levels implies that the user can assign

a very high overall priority level to an interrupt with a

low Natural Order Priority, thereby providing much

flexibility in designing applications that use a large

number of peripherals.

5.2

Interrupt Nesting

Interrupts, by default, are nestable. Any ISR that is in

progress may be interrupted by another source of

interrupt with a higher user-assigned priority level.

Interrupt nesting may be optionally disabled by

setting the NSTDIS control bit (INTCON1<15>).

When the NSTDIS control bit is set, all interrupts in

progress will force the CPU priority to level 7 by

setting IPL<2:0> = 111. This action will effectively

mask all other sources of interrupt until a RETFIE

instruction is executed. When interrupt nesting is

disabled, the user-assigned interrupt priority levels

will have no effect, except to resolve conflicts

between simultaneous pending interrupts.

The IPL<2:0> bits become read-only when interrupt

nesting is disabled. This prevents the user software

from setting IPL<2:0> to a lower value, which would

effectively re-enable interrupt nesting.

5.3

Traps

Traps can be considered as non-maskable, nestable

interrupts that adhere to a fixed priority structure.

Traps are intended to provide the user a means to

correct erroneous operation during debug and when

operating within the application. If the user does not

intend to take corrective action in the event of a trap

error condition, these vectors must be loaded with the

address of a software routine that will reset the device.

Otherwise, the trap vector is programmed with the

address of a service routine that will correct the trap

condition.

The dsPIC33F has four implemented sources of

non-maskable traps:

• Oscillator Failure Trap

• Address Error Trap

• Stack Error Trap

• Math Error Trap

•DMA Trap

Many of these trap conditions can only be detected

when they happen. Consequently, the instruction that

caused the trap is allowed to complete before

exception processing begins. Therefore, the user may

have to correct the action of the instruction that

caused the trap.

Each trap source has a fixed priority as defined by its

position in the IVT. An oscillator failure trap has the

highest priority, while an arithmetic error trap has the

lowest priority.

Table 5-2 contains information about the trap vector.

5.4

Generating a Software Interrupt

Any available interrupt can be manually generated by

user software (even if the corresponding peripheral is

disabled), simply by enabling the interrupt and then

setting the interrupt flag bit when required.

TABLE 5-2:

TRAP VECTORS

Vector Number

IVT Address

AIVT Address

Trap Source

0x000004

0x000084

Reserved

0x000006

0x000086

Oscillator Failure

0x000008

0x000088

Address Error

0x00000A

0x00008A

Stack Error

0x00000C

0x00008C

Math Error

0x00000E

0x00008E

DMA Error Trap

0x000010

0x000090

Reserved

0x000012

0x000092

Reserved

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