OP296 datasheet(40/88 Pages) AD

40 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 40 of 88

The endpoint nonlinearities illustrated in Figure 43 become

worse as a function of output loading. Most of the part’s

specifications assume a 10 kΩ resistive load to ground at the

DAC output. As the output is forced to source or sink more

current, the nonlinear regions at the top or bottom (respectively)

of Figure 43 become larger. Larger current demands can sig-

nificantly limit output voltage swing. Figure 44 and Figure 45

illustrate this behavior. Note that the upper trace in each of

these figures is valid only for an output range selection of

0 V-to-AVDD. In 0 V-to-VREF mode, DAC loading does not cause

high-side voltage drops as long as the reference voltage remains

below the upper trace in the corresponding figure. For example,

if AVDD = 3 V and VREF = 2.5 V, the high-side voltage is not be

affected by loads less than 5 mA. But somewhere around 7 mA,

the upper curve in Figure 45 drops below 2.5 V (VREF), indicating

that at these higher currents the output is not capable of

reaching VREF.

To reduce the effects of the saturation of the output amplifier at

values close to ground and to give reduced offset and gain errors,

the internal buffer can be bypassed. This is done by setting the

DBUF bit in the CFG841/CFG842 register. This allows a full

rail-to-rail output from the DAC, which should then be buffered

externally using a dual-supply op amp in order to get a rail-to-

rail output. This external buffer should be located as close as

physically possible to the DAC output pin on the PCB. Note that

the unbuffered mode works only in the 0 V to VREF range.

To drive significant loads with the DAC outputs, external

buffering may be required (even with the internal buffer

enabled), as illustrated in Figure 46. Table 11 lists some

recommended op amps.

ADuC841/

ADuC842

DAC0

DAC1

Figure 46. Buffering the DAC Outputs

The DAC output buffer also features a high impedance disable

function. In the chip’s default power-on state, both DACs are

disabled, and their outputs are in a high impedance state (or

three-state) where they remain inactive until enabled in

software. This means that if a zero output is desired during

power-up or power-down transient conditions, then a pull-

down resistor must be added to each DAC output. Assuming

this resistor is in place, the DAC outputs remain at ground

potential whenever the DAC is disabled.

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