OP296 datasheet(20/88 Pages) AD

20 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 20 of 88

UPPER 1792

BYTES OF

ON-CHIP XRAM

(DATA + STACK

FOR EXSP = 1,

DATA ONLY

FOR EXSP = 0)

256 BYTES OF

ON-CHIP DATA

RAM

(DATA +

STACK)

LOWER 256

BYTES OF

ON-CHIP XRAM

(DATA ONLY)

00H

FFH

00H

07FFH

CFG841.7 = 0

CFG842.7 = 0

100H

CFG841.7 = 1

CFG842.7 = 1

Figure 24. Extended Stack Pointer Operation

External Data Memory (External XRAM)

Just like a standard 8051 compatible core, the ADuC841/

ADuC842/ADuC843 can access external data memory by using

a MOVX instruction. The MOVX instruction automatically

outputs the various control strobes required to access the data

memory.

The parts, however, can access up to 16 MBytes of external data

memory. This is an enhancement of the 64 kBytes of external

data memory space available on a standard 8051 compatible core.

The external data memory is discussed in more detail in the

Hardware Design Considerations section.

Internal XRAM

The parts contain 2 kBytes of on-chip data memory. This

memory, although on-chip, is also accessed via the MOVX

instruction. The 2 kBytes of internal XRAM are mapped into

the bottom 2 kBytes of the external address space if the

CFG841/CFG842 bit is set. Otherwise, access to the external

data memory occurs just like a standard 8051. When using the

internal XRAM, Ports 0 and 2 are free to be used as general-

purpose I/O.

EXTERNAL

DATA

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

000000H

FFFFFFH

CFG841.0 = 0

CFG842.0 = 0

EXTERNAL

DATA

MEMORY

SPACE

(24-BIT

ADDRESS

SPACE)

000000H

FFFFFFH

CFG841.0 = 1

CFG842.0 = 0

0007FFH

000800H

2 kBYTES

ON-CHIP

XRAM

Figure 25. Internal and External XRAM

SPECIAL FUNCTION REGISTERS (SFRS)

The SFR space is mapped into the upper 128 bytes of internal

data memory space and is accessed by direct addressing only. It

provides an interface between the CPU and all on-chip periph-

erals. A block diagram showing the programming model of the

parts via the SFR area is shown in Figure 26.

All registers, except the program counter (PC) and the four

general-purpose register banks, reside in the SFR area. The SFR

registers include control, configuration, and data registers, which

provide an interface between the CPU and all on-chip peripherals.

128-BYTE

SPECIAL

FUNCTION

AREA

62-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

8051

COMPATIBLE

CORE

OTHER ON-CHIP

PERIPHERALS

TEMPERATURE

SENSOR

× 12-BIT DACs

SERIAL I/O

WDT

PSM

TIC

PWM

8-CHANNEL

12-BIT ADC

4-kBYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

2304 BYTES

RAM

Figure 26. Programming Model

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