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OP296 数据表(PDF) 78 Page - Analog Devices |
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OP296 数据表(HTML) 78 Page - Analog Devices |
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78 / 88 page  ADuC841/ADuC842/ADuC843 Rev. 0 | Page 78 of 88 TIMING SPECIFICATIONS1, 2, 3 Table 41. AVDD =2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted Parameter 32.768 kHz External Crystal ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1) Min Typ Max Unit tCK XTAL1 Period 30.52 µs tCKL XTAL1 Width Low 6.26 µs tCKH XTAL1 Width High 6.26 µs tCKR XTAL1 Rise Time 9 ns tCKF XTAL1 Fall Time 9 ns 1/tCORE ADuC842/ADuC843 Core Clock Frequency4 0.131 16.78 MHz tCORE ADuC842/ADuC843 Core Clock Period5 0.476 µs tCYC ADuC842/ADuC843 Machine Cycle Time6 0.059 0.476 7.63 µs 1 AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0, as shown in Figure 87. 2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 87. 3 CLOAD for all outputs = 80 pF, unless otherwise noted. 4 ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 2.09 MHz. 6 ADuC842/ADuC843 machine cycle time is nominally defined as 1/Core_CLK. Parameter Variable External Crystal ADuC841 CLOCK INPUT (External Clock Driven XTAL1) Min Typ Max Unit tCK XTAL1 Period 62.5 1000 ns tCKL XTAL1 Width Low 20 ns tCKH XTAL1 Width High 20 ns tCKR XTAL1 Rise Time 20 ns tCKF XTAL1 Fall Time 20 ns 1/tCORE ADuC841 Core Clock Frequency 0.131 20 MHz tCORE ADuC841 Core Clock Period 0.476 µs tCYC ADuC841 Machine Cycle Time 0.05 0.476 7.63 µs t CKH t CKL t CK t CKF t CKR Figure 86. XTAL1 Input DVDD – 0.5V 0.45V 0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD – 0.1V Figure 87. Timing Waveform Characteristics |
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