OP296 datasheet(21/88 Pages) AD

21 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 21 of 88

ACCUMULATOR SFR (ACC)

ACC is the accumulator register and is used for math opera-

tions including addition, subtraction, integer multiplication and

division, and Boolean bit manipulations. The mnemonics for

accumulator-specific instructions refer to the accumulator as A.

B SFR (B)

The B register is used with the ACC for multiplication and

division operations. For other instructions, it can be treated as a

general-purpose scratchpad register.

Stack Pointer (SP and SPH)

The SP SFR is the stack pointer and is used to hold an internal

RAM address that is called the top of the stack. The SP register

is incremented before data is stored during PUSH and CALL

executions. While the stack may reside anywhere in on-chip

RAM, the SP register is initialized to 07H after a reset, which

causes the stack to begin at location 08H.

As mentioned earlier, the parts offer an extended 11-bit stack

pointer. The 3 extra bits used to make up the 11-bit stack

pointer are the 3 LSBs of the SPH byte located at B7H.

Data Pointer (DPTR)

The data pointer is made up of three 8-bit registers named DPP

(page byte), DPH (high byte), and DPL (low byte). These are

used to provide memory addresses for internal and external

code access and for external data access. They may be manipu-

lated as a 16-bit register (DPTR = DPH, DPL), although INC

DPTR instructions automatically carry over to DPP, or as three

independent 8-bit registers (DPP, DPH, DPL). The parts support

dual data pointers. Refer to the Dual Data Pointer section.

Program Status Word (PSW)

The PSW SFR contains several bits reflecting the current status

of the CPU, as detailed in Table 5.

SFR Address

D0H

Power-On Default

00H

Bit Addressable

Yes

Table 5. PSW SFR Bit Designations

Bit

Name

Description

Carry Flag.

Auxiliary Carry Flag.

General-Purpose Flag.

RS1

RS0

RS1

RS0

Selected Bank

Overflow Flag.

General-Purpose Flag.

Parity Bit.

Power Control SFR (PCON)

The PCON SFR contains bits for power-saving options and

general-purpose status flags, as shown in Table 6.

SFR Address

87H

Power-On Default

00H

Bit Addressable

Table 6. PCON SFR Bit Designations

Bit No.

Name

Description

SMOD

Double UART Baud Rate.

SERIPD

I2C/SPI Power-Down Interrupt Enable.

INT0PD

INT0 Power-Down Interrupt Enable.

ALEOFF

Disable ALE Output.

GF1

General-Purpose Flag Bit.

GF0

General-Purpose Flag Bit.

Power-Down Mode Enable.

IDL

Idle Mode Enable.

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