OP296 datasheet(49/88 Pages) AD

49 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 49 of 88

Bit No.

Name

Description

I2CRS

I2C Reset Bit (Slave Mode Only).

Set by the user to reset the I2C interface.

Cleared by the user code for normal I2C operation.

I2CTX

I2C Direction Transfer Bit (Slave Mode Only).

Set by the MicroConverter if the interface is transmitting.

Cleared by the MicroConverter if the interface is receiving.

I2CI

I2C Interrupt Bit (Slave Mode Only).

Set by the MicroConverter after a byte has been transmitted or received.

Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).

I2CADD

I2C Address Register

Function

Holds the first I2C peripheral address for the part. It may be overwritten by user code. Application Note

uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in

detail.

SFR Address

9BH

Power-On Default

55H

Bit Addressable

I2CADD1

I2C Address Register

Function

Holds the second I2C peripheral address for the part. It may be overwritten by user code.

SFR Address

91H

Power-On Default

7FH

Bit Addressable

I2CADD2

I2C Address Register

Function

Holds the third I2C peripheral address for the part. It may be overwritten by user code.

SFR Address

92H

Power-On Default

7FH

Bit Addressable

I2CADD3

I2C Address Register

Function

Holds the fourth I2C peripheral address for the part. It may be overwritten by user code.

SFR Address

93H

Power-On Default

7FH

Bit Addressable

I2CDAT

I2C Data Register

Function

Written by the user to transmit data over the I2C interface or read by user code to read data just

received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and

the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.

SFR Address

9AH

Power-On Default

00H

Bit Addressable

The main features of the MicroConverter I2C interface are

•

Only two bus lines are required: a serial data line (SDATA)

and a serial clock line (SCLOCK).

•

An I2C master can communicate with multiple slave

devices. Because each slave device has a unique 7-bit

address, single master/slave relationships can exist at all

times even in a multislave environment.

•

Ability to respond to four separate addresses when

operating in slave mode.

OP296 数据表(PDF) 49 Page - Analog Devices

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OP296 数据表(PDF) 49 Page - Analog Devices

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