AD6620SSLASHPCB datasheet(27/44 Pages) AD

27 / 44 page

AD6620

–27–

REV. A

If the AD6620s to be synchronized have identical decimation,

then latency through the filter stages will be matched and output

data rates for the Sync master’s filter stages will match the cor-

responding filter stages of the slave.

SYNC M/S

MASTER

SLAVE

SYNC CIC

SYNC RCF

MASTER

SLAVE

Figure 42. SYNC_CIC, SYNC_RCF Pins

The three SYNC inputs to the control block originate from the

same three bidirectional pads from which the three SYNC out-

puts are driven. When the AD6620 is a SYNC MASTER, the

internal circuitry that generates the SYNC pulse outputs is

enabled to the pads. When the AD6620 is a SYNC SLAVE, the

internally produced SYNC pulses are three-stated, and the pads

are driven from an external input. The capacitance on these pins

must be closely monitored since the master responds to the

same SYNC pulse as the slave (its own pulse). There is no input

requirement to the relative phases of these SYNC pulses. In the

absence of SYNC pulses each state machine will free run so the

latter decimation filters can be reliably synchronized by the

SYNC pulses of an earlier stage. However, when sync pulses are

provided externally, setup-and-hold times must be met for each

respective input.

CONTROL REGISTERS AND ON-CHIP RAM

The AD6620 provides a choice of two control ports. It has an

8-bit generic microprocessor port that is used for configuring

the device at boot up and dynamically reconfiguring the AD6620

in the system. It also has a synchronous serial port that can also

dynamically reconfigure the AD6620 for the desired system

operation. All control registers are available from both the serial

port and the microprocessor port. These control methods are

nonexclusive and the two ports can be used simultaneously. If

simultaneous access occurs, the serial port is given precedence

over the microprocessor port unless a micro cycle is already

under way. The microprocessor port deasserts the RDY signal

and waits until the serial access is completed for Mode 0. The

microprocessor port does not assert DTACK for Mode 1 until

the serial access is completed.

Filter Phase Synchronization

Like the NCO, the AD6620 filter stages have phase synchroni-

zation circuitry enabling multiple AD6620s to be used in appli-

cations such as diversity antennas and phased array systems.

For any fSAMP, there are MCIC2 possible phases of fSAMP2 at the

output of the CIC2 stage. Similarly, at the output of the CIC5

stage, there are MCIC5 possible phases of fSAMP5. This means that

at the output of the CIC stages there is already MCIC2

× M

CIC5

possible phases of the filtered data. Additional phase uncertainty

is introduced by decimation done in the RCF. At the output of

the AD6620 there are a total of MCIC2

× M

CIC5

× M

RCF possible

output phases of the data.

In diversity systems using multiple AD6620s, it is necessary to

ensure that the output of each AD6620 in the system is in phase.

A variety of system issues (e.g., not bringing the AD6620s on

line at the same time, excessive digital noise) could cause the

AD6620s to start out-of-phase or to drift out-of-phase as the

system runs. To achieve output phase coherence in such systems

the SYNC_CIC and SYNC_RCF pins are provided.

The function of these pins is controlled by the SYNC_M/S bit

in the Mode Control Register at address 300 hex of internal

address space. When the SYNC_M/S bit is high, SYNC_CIC

and SYNC_RCF provide synchronization pulses on the rising

edge of CLK. When the SYNC_M/S bit is low, SYNC_CIC and

SYNC_RCF accept external synchronization pulses sampled on

the rising edge of clock. This pulse edge synchronizes the CIC2,

CIC5 and RCF filter stages of all AD6620 in the chain.

Below is an example of the output SYNC pulse waveforms.

The SYNC_NCO pulse is not shown and is described in the

preceding NCO Synchronization section. Each SYNC_RCF

output pulse is concurrent with a SYNC_CIC pulse. The

SYNC_RCF output pulse can be connected to the SYNC_CIC,

and SYNC_RCF inputs of another AD6620 to achieve full

decimation synchronization.

CLK

SYNC CIC

SYNC RCF

Figure 41. SYNC Output Pulses

In the example above, MCIC2 = 3, and MCIC5 = 1 as evidenced

by the SYNC_CIC pulses that occur every 3 CLK cycles

(MCIC2

× MCIC5). MRCF = 3, resulting in SYNC_RCF pulses

that are one third as frequent as the SYNC_CIC pulses. In this

example full rate input timing is employed such that the input

data rate equals the clock rate.

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