AD6620SSLASHPCB datasheet(43/44 Pages) AD

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AD6620

–43–

REV. A

CLOCK

DVOUT1

DVOUT2

DVOUT3

DVOUT4

AD6620–1

AD6620–2

AD6620–3

AD6620–4

SELECTOR

OUTPUT

Figure 59. Timing for Parallel Processing

INPUT LATCHING

DOUT1

CLOCK

DVOUT1

DOUT2

CLOCK

DVOUT2

DOUT3

CLOCK

DVOUT3

DOUT4

CLOCK

DVOUT4

INPUT LATCHING

OUTPUT

LATCHING

Figure 58. Parallel Processing Output Selector

In the Output Selector above each of the DVOUT lines is ANDed

with main clock. This allows the data out of each of the AD6620s

to be properly latched into the input latches. The DVOUT line is

also responsible for placing the latched outputs on the internal

bus at the proper time. This data is then latched in the output

latch using the internal ORed clocking signals.

The timing for these events is shown in Figure 59. As shown,

the system clock is run at the specified rate. Then the RCF

timing control state machine is responsible for generating the

appropriate sync pulses. When each AD6620 completes its SOP

computation, it generates the DVOUT pulses shown below. Concur-

rently, each chip places its IQ data on the output pins of that

device. With this data, the output selector state machine com-

bines all of the data and places the data on the output bus.

Using the AD6620 in a Narrow Band System

A typical interconnection between the AD6600, AD6620 and a

General Purpose DSP is shown in Figure 65. This is an example

of an IF sampling narrow-band system and offers many techni-

cal and cost advantages over traditional solutions. In this example,

the AD6620 is in Diversity Channel Real Mode, with the AD6600

sampling a diversity antenna on its B channel. The AD6620

performs floating-point to fixed-point conversion, digital tuning,

digital filtering and decimation of the A/D output data.

MAIN

INPUT

DIVERSITY

INPUT

2 CLK

A/B OUT

3 RSSI BITS

11 DATA BITS

ENCODE

SCLK

SDI

SDO

SDFS

CLK

A/B

E[2...0]

IN[15...5]

AD6620

AD6600

SCLK

SDO

SDI

SDFS

DSP

Figure 60. Implementation of a Narrow Band Receiver

The 2

× CLK on the AD6600 is used as the processing CLK of

the AD6620. The use of this faster clock allows the RCF filter

to process up to twice as many taps per sample. The increased

number of taps available helps to improve the filter characteris-

tics. In some applications an even faster processing clock may be

necessary to allow for improved digital filter performance. In

this case the A/B pin of the AD6620 must be toggled when each

channel input is to be sampled.

For most narrow-band uses of the AD6600/AD6620 combina-

tion, a high oversampling ratio is desired. This spreads the

quantization noise of the A/D over a wider spectrum and allows

the digital filtering of the AD6620 to remove much of this noise.

This effectively increases the SNR of the AD6600. This process

of oversampling and digital filtering is called “process gain”

and its contribution to SNR can be calculated from the equa-

tion below.

Sample Rate of Channel

Signal Bandwidth









10 log

The process of oversampling can also provide the benefit of

lowering the noise floor of the A/D. This can increase the effec-

tive dynamic range of a receiver if the sampling rate is chosen

such that the signal harmonics and/or intermodular distortion

(IMD) products fall out of the band of interest. In this case

these spurs could be filtered by the AD6620 and the quantiza-

tion noise would be the dominant dynamic range limitation of

the AD6600/AD6620 receiver solution.

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