AD6620SSLASHPCB datasheet(38/44 Pages) AD

38 / 44 page

AD6620

–38–

REV. A

APPLICATIONS

EVALUATION BOARD

An evaluation board is available for the AD6620. This evalua-

tion board comes complete with an AD6620 and interfaces to a

PC through the printer port. The evaluation board comes com-

plete with software to drive the evaluation board and to design

optimized filters for use with the AD6620. The evaluation board

includes a high speed data interface that mates directly with

evaluation boards for high performance converters such as the

AD6600 and AD6640, allowing digital receivers to be bread-

boarded with only an external RF/IF converter and an interface

to the DSP.

The control software allows access to all of the internal registers

to provide complete programming of the device in a lab setting.

The software can process high speed data as well as digitally

filtered data from the AD6620 allowing analysis of both pre and

post filter channel characteristics. The controlling software can

also be used to verify the filter performance by sweeping the NCO,

greatly simplifying verification of any given filter design.

AD6620

HI SPEED

DATA

HEADER

LATCH

FIFO

PC PRINTER PORT

LATCH

TRANSCEIVER

Figure 47. Evaluation Board Block Diagram

As shown in the block diagram below, the high speed data into

the evaluation board is sent to both the AD6620 and the by-pass

latches. On the output of the AD6620, data is available in either

serial or parallel mode. In serial mode, data may be sent directly

to a DSP for system bread-boarding. In parallel mode, the data

may be sent to the on-board FIFO for spectral analysis by the

included software. For additional information, refer to the evalua-

tion board manual.

FILTER DESIGN

The AD6620 implements a pair of cascaded CIC filters with a

sum of products FIR filter. The frequency characteristics of the

CIC filters have already been documented. Additional reading

on this class of filters can be found in “An Economical Class of

Digital Filters for Decimation and Interpolation,” by Eugene B.

Hogenauer, IEEE Transactions on Acoustics, Speech, and Signal

Processing, Volume ASSP-29, Number 2, April 1981.

The characteristics of the FIR filter are fully programmable.

The coefficients of this filter may be generated in any number

of ways, using standard procedures such as Parks-McClellan.

Available software from Analog Devices that assists in the design

of filters for this product. This software allows comparison

between different distributions of decimation. The software

works independently of the evaluation board, but easily allows

transfer of design data directly to the evaluation board for

immediate verification of the designed filter.

The normal procedure for designing a filter for the chip is as

shown in the flow chart. First, the desired characteristics must

be determined based on the receive channel requirements. The

decimation rates for the CIC filters must then be selected such

that their performance is near that of the desired channel require-

ments. Finally, an algorithm such as the Parks-McClellan or

Remez exchange is used to compute the final spectral require-

ments, including droop correction for passband loss of the CIC

filters. If the designed filter meets the requirements, then the

filter is acceptable. If not, another combination of CIC filter

decimation must be examined. Tables III and IV greatly simplify

distribution and selection of CIC requirements. The filter

software available from Analog Devices helps to automate

this procedure.

SELECT FILTER

REJECTION

REQUIREMENTS

DOES CIC2 FILTER

PROTECT ENOUGH

BANDWIDTH?

SELECT

DECIMATION

RATE FOR CIC5

DESIGN RCF WITH

REMEZ EXCHANGE

YES

SELECT

DECIMATION

RATE FOR CIC2

DOES CIC5 FILTER

PROTECT ENOUGH

BANDWIDTH?

DOES COMPOSITE

FILTER PROVIDE

THE DESIRED

RESULTS?

YES

Figure 48. Diagram of Filter Design Software

SERIAL BUFFERING

The AD6620 serial outputs are designed to operate at very high

speed. As such, care must be taken when driving the serial output

lines. These high speed lines must be treated as transmission

lines. Critical lines include the SCLK, SDFS, SDFE, SDI and

SDO. It is recommended that these lines be series source termi-

nated with the characteristic impedance of the driven line. If the

lines are longer than a few inches, digital line buffers should be

used as shown below. Buffering in this manner will prevent

reflections on the serial lines from disrupting operation of the

AD6620. A good reference on transmission lines is found in the

“MECL System Design Handbook” by Motorola Inc., Stock

code HB205R1/D.

AD6620

SCLK

SDO

SDFS

SCLK

SDO

SDFS

Figure 49. Serial Line Buffering and Series Source

Termination

DSP/SHARC INTERFACING

With little effort, the AD6620 will interface to nearly all indus-

try standard DSPs, as shown in the figure below. The figures

below show operation in TDM applications as well as in serial

slave mode.

In TDM mode the first AD6620 is configured to be the master.

This chip is the first to access the serial data bus. When the

master has data available in its output shifters, it generates an

SDFS telling the DSP that serial data will follow. At this point,

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