Enhanced Product

AD9512-EP

Rev. 0 | Page 3 of 20

SPECIFICATIONS

CLOCK INPUTS

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUTS (CLK1, CLK2)1

Input Frequency

0

1.6

GHz

Input Sensitivity

1502

mV p-p

Jitter performance can be improved with higher slew

rates (greater swing).

Input Level

23

V p-p

Larger swings turn on the protection diodes and can

degrade jitter performance.

1.45

1.6

1.7

V

Self-biased; enables ac coupling; at full temperature range

1.5

1.6

1.7

V

At −40°C to +85°C.

1.3

1.8

V

With 200 mV p-p signal applied; dc-coupled.

Input Sensitivity, Single-Ended

150

mV p-p

CLK2 ac-coupled; CLK2B ac bypassed to RF ground.

Input Resistance

4.0

4.8

5.6

kΩ

Self-biased.

Input Capacitance

2

pF

1

CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.

2

With a 50 Ω termination, this is −12.5 dBm.

3

With a 50 Ω termination, this is +10 dBm.

CLOCK OUTPUTS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2; Differential

Output level 0x3D (0x3E) (0x3F)[3:2] = 10b

Output Frequency

1200

MHz

See Figure 10

V

V

660

810

965

mV

LVDS CLOCK OUTPUTS

Termination = 100 Ω differential; default

OUT3, OUT4; Differential

Output level 0x40 (0x41)[2:1] = 01b

3.5 mA termination current

Output Frequency

800

MHz

See Figure 11

250

360

450

mV

25

mV

1.05

1.23

1.375

V

At full temperature range

1.125

1.23

1.375

V

At −40°C to +85°C

25

mV

14

24

mA

Output shorted to GND

CMOS CLOCK OUTPUTS

OUT3, OUT4

Single-ended measurements;

B outputs: inverted, termination open

Output Frequency

250

MHz

With 5 pF load each output; see Figure 12

V

@ 1 mA load

0.1

V

@ 1 mA load