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AD9512UCPZ-EP-R7 数据表(PDF) 9 Page - Analog Devices |
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AD9512UCPZ-EP-R7 数据表(HTML) 9 Page - Analog Devices |
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9 / 20 page  Enhanced Product AD9512-EP Rev. 0 | Page 9 of 20 Parameter Min Typ Max Unit Test Conditions/Comments CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s) All LVPECL = 50 MHz Interferer(s) CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 275 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz 400 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) LVDS (OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 374 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output Off) Interferer(s) CLK1 = 400 MHz 555 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz Interferer(s) CMOS (OUT4) = 50 MHz (B Output On) Interferer(s) |
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