AD9512UCPZ-EP-R7 datasheet(11/20 Pages) AD

11 / 20 page

Enhanced Product

AD9512-EP

Rev. 0 | Page 11 of 20

SYNC STATUS PIN

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

Output Voltage High (VOH)

2.7

Output Voltage Low (VOL)

0.4

POWER

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-UP DEFAULT MODE POWER DISSIPATION

550

600

Power-up default state; does not include power

dissipated in output load resistors. No clock.

POWER DISSIPATION

800

All outputs on. Three LVPECL outputs @ 800 MHz,

two CMOS out @ 62 MHz (5 pF load). Does not include

power dissipated in external resistors.

850

All outputs on. Three LVPECL outputs @ 800 MHz,

two CMOS out @ 125 MHz (5 pF load). Does not include

power dissipated in external resistors.

Full Sleep Power-Down

Maximum sleep is entered by setting 0x0A[1:0] = 01b

and 0x58[4] = 1b. This powers off all band gap

references. Does not include power dissipated in

terminations.

Power-Down (PDB)

Set FUNCTION pin for PDB operation by setting

0x58[6:5] = 11b. Pull PDB low. Does not include

power dissipated in terminations.

POWER DELTA

CLK1, CLK2 Power-Down

Divider, DIV 2 to 32 to Bypass

For each divider.

LVPECL Output Power-Down (PD2, PD3)

For each output. Does not include dissipation

in termination (PD2 only).

LVDS Output Power-Down

110

For each output.

CMOS Output Power-Down (Static)

For each output. Static (no clock).

CMOS Output Power-Down (Dynamic)

115

150

190

For each CMOS output, single-ended. Clocking at

62 MHz with 5 pF load.

CMOS Output Power-Down (Dynamic)

125

165

210

For each CMOS output, single-ended. Clocking at

125 MHz with 5 pF load.

AD9512UCPZ-EP-R7 数据表(PDF) 11 Page - Analog Devices

AD9512UCPZ-EP-R7 数据表(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载