Enhanced Product

AD9512-EP

Rev. 0 | Page 5 of 20

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS-TO-CMOS OUT

Everything the same; different logic type

158

353

506

ps

LVDS to CMOS on same part

1

The measurements are for CLK1. For CLK2, add approximately 25 ps.

2

This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.

3

This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.

CLOCK OUTPUT PHASE NOISE

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK1-TO-LVPECL ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT = 622.08 MHz

Input slew rate > 1 V/ns

Divide Ratio = 1

@ 10 Hz Offset

−125

dBc/Hz

@ 100 Hz Offset

−132

dBc/Hz

@ 1 kHz Offset

−140

dBc/Hz

@ 10 kHz Offset

−148

dBc/Hz

@ 100 kHz Offset

−153

dBc/Hz

>1 MHz Offset

−154

dBc/Hz

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

@ 10 Hz Offset

−128

dBc/Hz

@ 100 Hz Offset

−140

dBc/Hz

@ 1 kHz Offset

−148

dBc/Hz

@ 10 kHz Offset

−155

dBc/Hz

@ 100 kHz Offset

−161

dBc/Hz

>1 MHz Offset

−161

dBc/Hz

CLK1 = 622.08 MHz, OUT = 38.88 MHz

Divide Ratio = 16

@ 10 Hz Offset

−135

dBc/Hz

@ 100 Hz Offset

−145

dBc/Hz

@ 1 kHz Offset

−158

dBc/Hz

@ 10 kHz Offset

−165

dBc/Hz

@ 100 kHz Offset

−165

dBc/Hz

>1 MHz Offset

−166

dBc/Hz

CLK1 = 491.52 MHz, OUT = 61.44 MHz

Divide Ratio = 8

@ 10 Hz Offset

−131

dBc/Hz

@ 100 Hz Offset

−142

dBc/Hz

@ 1 kHz Offset

−153

dBc/Hz

@ 10 kHz Offset

−160

dBc/Hz

@ 100 kHz Offset

−165

dBc/Hz

>1 MHz Offset

−165

dBc/Hz

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

@ 10 Hz Offset

−125

dBc/Hz

@ 100 Hz Offset

−132

dBc/Hz

@ 1 kHz Offset

−140

dBc/Hz

@ 10 kHz Offset

−151

dBc/Hz

@ 100 kHz Offset

−157

dBc/Hz

>1 MHz Offset

−158

dBc/Hz