1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,

Dividers, Five Outputs

Enhanced Product

AD9512-EP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2012 Analog Devices, Inc. All rights reserved.

FEATURES

Two 1.6 GHz, differential clock inputs

5 programmable dividers, 1 to 32, all integers

3 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter: 275 fs rms

Serial control port

Space-saving 48-lead LFCSP

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC

standard)

Military temperature range (−55°C to +85°C)

Controlled manufacturing baseline

1 assembly/test site

1 fabrication site

Enhanced product change notification

Qualification data available on request

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Defense and aerospace applications

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9512-EP provides a multi-output clock distribution

in a design that emphasizes low jitter and low phase noise to

maximize data converter performance. Other applications

with demanding phase noise and jitter requirements can also

benefit from this part.

There are five independent clock outputs. Three outputs are

LVPECL (1.2 GHz), and two are selectable as either LVDS

(800 MHz) or CMOS (250 MHz) levels.

Each output has a programmable divider that can be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output can be varied by means

of a divider phase select function that serves as a coarse timing

adjustment.

The AD9512-EP is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9512-EP is available in a 48-lead LFCSP and can be

operated from a single 3.3 V supply. The temperature range is

−55°C to +85°C.

Additional application and technical information can be found

in the AD9512 data sheet.

Note that the delay block element that exists in Channel 4 of the

AD9512 standard product is not supported in this AD9512-EP

version.

SYNC

STATUS

SYNC

STATUS

SCLK

SDIO

SDO

CSB

SERIAL

CONTROL

PORT

FUNCTION

SYNCB,

RESETB

PDB

DSYNC

DSYNCB

DETECT

SYNC

VREF

RSET

AD9512-EP

GND

VS

CLK1

CLK1B

CLK2

CLK2B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

OUT0

OUT0B

LVPECL

/1, /2, /3... /31, /32

OUT1

OUT1B

LVPECL

/1, /2, /3... /31, /32

OUT2

OUT2B

LVPECL

/1, /2, /3... /31, /32

OUT3

OUT3B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT4

OUT4B

LVDS/CMOS

/1, /2, /3... /31, /32