AD9512-EP

Enhanced Product

Rev. 0 | Page 10 of 20

SERIAL CONTROL PORT

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB, SCLK (INPUTS)

CSB and SCLK have 30 kΩ

internal pull-down resistors

Input Logic 1 Voltage

2.0

V

Input Logic 0 Voltage

0.8

V

Input Logic 1 Current

110

µA

Input Logic 0 Current

1

µA

Input Capacitance

2

pF

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

V

Input Logic 0 Voltage

0.8

V

Input Logic 1 Current

10

nA

Input Logic 0 Current

10

nA

Input Capacitance

2

pF

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

V

Output Logic 0 Voltage

0.4

V

TIMING

25

MHz

16

ns

16

ns

2

ns

1

ns

6

ns

2

ns

3

ns

FUNCTION PIN

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

The FUNCTION pin has a 30 kΩ internal pull-down resistor.

This pin should normally be held high. Do not let input float.

Logic 1 Voltage

2.0

V

Logic 0 Voltage

0.8

V

Logic 1 Current

110

µA

Logic 0 Current

1

µA

Capacitance

2

pF

RESET TIMING

Pulse Width Low

50

ns

SYNC TIMING

Pulse Width Low

1.5

High speed clock cycles

High speed clock is CLK1 or CLK2, whichever is being used

for distribution.