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AD9512UCPZ-EP-R7 数据表(PDF) 8 Page - Analog Devices |
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AD9512UCPZ-EP-R7 数据表(HTML) 8 Page - Analog Devices |
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8 / 20 page  AD9512-EP Enhanced Product Rev. 0 | Page 8 of 20 CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz, 40 fs rms BW = 12 kHz to 20 MHz (OC-12) Any LVPECL (OUT0 to OUT2) = 622.08 MHz, Divide Ratio = 1 CLK1 = 622.08 MHz 55 fs rms BW = 12 kHz to 20 MHz (OC-3) Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 100 MHz Interferer(s) CLK1 = 400 MHz 222 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both LVDS (OUT3, OUT4) = 50 MHz Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) Interferer(s) CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Interferer(s) Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) Interferer(s) LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 264 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz Interferer(s) All LVPECL = 50 MHz Interferer(s) |
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