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ADA4661-2ARMZ-R7 数据表(PDF) 22 Page - Analog Devices

部件名 ADA4661-2ARMZ-R7
功能描述  18 V, Precision, 725 A, 4 MHz, CMOS RRIO Operational Amplifier
PDF  32 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADA4661-2ARMZ-R7 数据表(HTML) 22 Page - Analog Devices

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ADA4661-2
Data Sheet
Rev. 0 | Page 22 of 32
APPLICATIONS INFORMATION
Figure 70. Simplified Schematic
The ADA4661-2 is a low power, rail-to-rail input and output,
precision CMOS amplifier that operates over a wide supply
voltage range of 3 V to 18 V. This amplifier uses the Analog
Devices DigiTrim technique to achieve a higher degree of
precision than is available from other CMOS amplifiers. The
DigiTrim technique is a method of trimming the offset voltage
of an amplifier after assembly. The advantage of postpackage
trimming is that it corrects any offset voltages caused by
mechanical stresses of assembly. To achieve a rail-to-rail input
and output range with very low supply current, the ADA4661-2
uses unique input and output stages.
INPUT STAGE
Figure 70 shows the simplified schematic of the ADA4661-2.
The amplifier uses a three-stage architecture with a fully
differential input stage to achieve excellent dc performance
specifications.
The input stage comprises two differential transistor pairs—
a NMOS pair (M1, M2) and a PMOS pair (M3, M4)—and
folded-cascode transistors (M5 to M12). The input common-
mode voltage determines which differential pair is active. The
PMOS differential pair is active for most of the input common-
mode range. The NMOS pair is required for input voltages up
to and including the upper supply rail. This topology allows the
amplifier to maintain a wide dynamic input voltage range and
maximize signal swing to both supply rails.
The proprietary high voltage protection circuitry in the
ADA4661-2 minimizes the common-mode voltage changes
seen by the amplifier input stage for most of the input common-
mode range. This results in the amplifier having excellent
disturbance rejection when operating in this preferred
common-mode range. The performance benefits of operating
within this preferred range are shown in the PSRR vs. VCM (see
Figure 17), CMRR vs. VCM (see Figure 14), and VOS vs. VCM
graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). The CMRR performance benefits of the reduced
common-mode range are guaranteed at final test and shown in the
electrical characteristics (see Table 2 to Table 4).
For most of the input common-mode voltage range, the PMOS
differential pair is active. When the input common-mode
voltage is within a few volts of the power supplies, the input
transistors are exposed to these voltage changes. As the
common-mode voltage approaches the positive power supply,
the active differential pair changes from the PMOS pair to the
NMOS pair. Differential pairs commonly exhibit different offset
voltages. The handoff of control from one differential pair to the
other creates a step like characteristic that is visible in the VOS vs.
VCM graphs (see Figure 8, Figure 11, Figure 12, Figure 13, Figure 15,
and Figure 16). This characteristic is inherent in all rail-to-rail
input amplifiers that use the dual differential pair topology.
Additional steps in the VOS vs. VCM graphs are visible as the
common-mode voltage approaches the negative power supply.
These changes are a result of the load transistors (M5, M6)
running out of headroom. As the load transistors are forced into
the triode region of operation, the mismatch of their drain
impedance becomes a significant portion of the amplifier offset.
This effect can also be seen in the VOS vs. VCM graphs (see Figure 8,
Figure 11, Figure 12, Figure 13, Figure 15, and Figure 16).
Current Source I2 drives the PMOS transistor pair. As the input
common-mode voltage approaches the upper power supply,
this current is reduced to zero. At the same time, a replica
current source, I1, is increased from zero to enable the NMOS
transistor pair.
The ADA4661-2 achieves its high performance specifications by
using low voltage MOS devices for its differential inputs. These
low voltage MOS devices offer excellent noise and bandwidth
per unit of current. The input stage is isolated from the high
V+
V–
+IN x
OUT x
R1
D1
M1
M2
M3
M11
M12
C1
C3
C2
V1
M9
M10
M7
M8
Q1
Q2
M5
HIGH VOLTAGE PROTECTION
M6
M15
M21
M22
M16
M13
M14
M19
M20
M17
M18
M4
D2
R2
I1
I3
I2
–IN x
HIGH VOLTAGE PROTECTION



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