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ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 36 of 44

Power-Up Procedure for Systems with Multiple Devices

That Use Clock Generated from Microcontroller

For polyphase energy meters in which the microcontroller

generates the clock signal used by all ADE7912/ADE7913

devices (see Figure 36), the power-up procedure is as follows:

1. Supply VDD to the ADE7912/ADE7913 devices. To ensure

that the ADE7912/ADE7913 devices start functioning

correctly, the supply must reach 3.3 V − 10% in less than

23 ms from approximately a 2.6 V level.

2. Generate the clock signal from the microcontroller to all

ADE7912/ADE7913 devices.

3. The dc-to-dc converters power up and supply the isolated

side of the ADE7912/ADE7913 devices. The Σ-Δ

modulators become functional. This process takes

approximately 100 ms to execute when the recommended

capacitors on the VDDISO, LDO, and REF pins described in

Table 9 are used. After this time, the isolated sides of the

ADE7912/ADE7913 devices are fully functional.

4. Read the STATUS0 registers of the ADE7912/ADE7913

devices until Bit 0 (RESET_ON) is cleared to 0, indicating

that the nonisolated side of the ADE7912/ADE7913 devices

is fully functional with default settings. This happens

approximately 20 ms after the clock signal is provided.

5. Initialize the CONFIG register of the ADE7912/ADE7913

devices with Bit 0 (CLKOUT_EN) cleared to 0 to avoid

generating an unnecessary clock at the CLKOUT/DREADY

pin. Select one ADE7912/ADE7913 device (Phase C

ADE7912/ADE7913 in Figure 36, for example) and

connect its CLKOUT/DREADY pin to an external

interrupt I/O pin of the microcontroller.

6. Initialize EMI_CTRL, the emissions control register, of all

ADE7912/ADE7913 devices.

7. Execute a SYNC_SNAP = 0x01 write broadcast to

synchronize all the ADE7912/ADE7913 devices of the

meter (see the Synchronizing Multiple ADE7912/ADE7913

Devices sections for details).

8. Execute a lock = 0xCA write broadcast to protect the

configuration registers of all ADE7912/ADE7913 devices.

See the Protecting the Integrity of Configuration Registers

section.

9. Every couple of seconds, disable the registers protection,

execute a SYNC_SNAP = 0x02 write broadcast to read the

COUNTER1 and COUNTER0 registers of every

ADE7912/ADE7913, and verify if resynchronization is

necessary. Resynchronize the ADE7912/ADE7913 devices

that are out of synchronization (see the Synchronizing

Multiple ADE7912/ADE7913 Devices section) and then

reenable protection of the configuration registers.

HARDWARE RESET

The ADE7912/ADE7913 do not have a dedicated reset pin.

Instead, while the SCLK pin is receiving the serial clock, the CS

and MOSI pins can be kept low by executing a SPI broadcast

write operation in which the lines are kept low for 64 SCLK

cycles. This is equivalent to sending eight bytes equal to 0x00 to

the ADE7912/ADE7913 to accomplish a hardware reset.

During a hardware reset, all the registers are set to their default

values and the dc-to-dc converter is shut down. This procedure

can be done simultaneously for all ADE7912/ADE7913 devices

in a polyphase energy meter. At the end of the reset period, the

ADE7912/ADE7913 clears Bit 0 (RESET_ON) to 0 in the

STATUS0 register. At this point, one of the procedures

described in the Power-Up and Initialization Procedures

section must be followed to initialize the ADE7912/ADE7913

devices correctly.

SOFTWARE RESET

Bit 6 (SWRST) in the CONFIG register manages the software

reset functionality. The default value of this bit is 0. If this bit is

set to 1, the ADE7912/ADE7913 enter the software reset state.

In this state, all the internal registers are reset to their default

values. The dc-to-dc converter continues to function. When the

software reset ends, Bit 6 (SWRST) in the CONFIG register

clears automatically to 0 and Bit 0 (RESET_ON) in the STATUS0

protected using a lock = 0xCA register write, first unlock the

registers by writing lock = 0x9C and then write to the CONFIG

At this point, one of the procedures described in the Power-Up

and Initialization Procedures section must be followed to

initialize the ADE7912/ADE7913 correctly.

POWER-DOWN MODE

There are situations in which the ADCs of the ADE7912/

ADE7913 do not need to function and it is desirable to lower

the current consumption of the device. When set to 1, Bit 2

(PWRDWN_EN) in the CONFIG register turns off the dc-to-

dc converter and shuts down the Σ-Δ modulators. Although the

ADE7912/ADE7913 configuration registers maintain their

values, the IWV, V1WV, and V2WV ADC output registers are

in an undefined state. If PWRDWN_EN is cleared to 0, the

default value, the dc-to-dc converter is functional and the Σ-Δ

modulators are active.

If the microcontroller generates the clock to all ADE7912/

ADE7913 devices (the configuration shown in Figure 36), the

current consumption can be further reduced by shutting down

the clock. The ADE7912/ADE7913 stop functioning. When the

clock is restarted, as a good programming practice, execute a

hardware reset to restart the ADE7912/ADE7913.

In systems in which the CLKOUT/DREADY pin of one ADE7912/

ADE7913 device is used to clock other ADE7912/ADE7913

devices (the configuration shown in Figure 35, Figure 37, and

Figure 38), lower current consumption of the ADE7912/ADE7913

devices can be achieved by clearing Bit 0 (CLKOUT_EN) to 0 in

the CONFIG register.

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