ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 6 of 44

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Signal-to-Noise-and-Distortion Ratio, SINAD

72

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

74

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

77

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

78

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

Total Harmonic Distortion, THD

−83

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

−83

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

−85

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

−85

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

Spurious-Free Dynamic Range, SFDR

86

dBFS

ADC_FREQ = 8 kHz, BW = 3300 Hz

86

dBFS

ADC_FREQ = 8 kHz, BW = 2000 Hz

87

dBFS

ADC_FREQ = 2 kHz, BW = 825 Hz

87

dBFS

ADC_FREQ = 2 kHz, BW = 500 Hz

CLKIN2

All specifications for CLKIN = 4.096 MHz

Input Clock Frequency, CLKIN

3.6

4.096

4.21

MHz

CLKIN Duty Cycle

45

50

55

%

XTAL1 Logic Inputs

2.4

V

0.8

V

XTAL1 Total Capacitance3

40

pF

XTAL2 Total Capacitance3

40

pF

CLKOUT Delay from XTAL14

100

ns

LOGIC INPUTS—MOSI, SCLK, CS

2.4

V

0.8

V

15

nA

10

pF

LOGIC OUTPUTS—CLKOUT/DREADY AND MISO

2.5

V

0.4

V

POWER SUPPLY

For specified performance

VDD Pin

2.97

3.63

V

Minimum = 3.3 V − 10%; maximum = 3.3 V + 10%

12.5

19

mA

Bit 2 (PWRDWN_EN) in CONFIG register cleared to 0

2.7

3

mA

Bit 2 (PWRDWN_EN) in CONFIG register set to 1

50

μA

Bit 2 (PWRDWN_EN) in CONFIG register set to 1

and no CLKIN signal at XTAL1 pin

the ceramic capacitor connected between the pin and GND. See the ADE7912/ADE7913 Clock section for more details.

when CLKOUT functionality is enabled.