ADE7913 datasheet(31/44 Pages) AD

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Data Sheet

ADE7912/ADE7913

Rev. 0 | Page 31 of 44

POWER MANAGEMENT

DC-TO-DC CONVERTER

The dc-to-dc converter section of the ADE7912/ADE7913 works

on principles that are common to most modern power supply

designs. VDD power is supplied to an oscillating circuit that

drives the primary side of a chip scale air core transformer.

Power is transferred to the secondary side, where it is rectified

to a 3.3 V dc voltage. This voltage is then supplied to the ADC

side section through a 2.5 V LDO regulator.

The internal dc-to-dc converter state of the ADE7912/ADE7913

is controlled by the input, VDD. In normal operation mode,

maintain VDD between 2.97 V and 3.63 V.

The block diagram of the isolated dc-to-dc converter is shown

in Figure 47. The ADE7912/ADE7913 primary supply voltage

VDD input supplies an alternative current (ac) source. The ac

signal passes through a chip scale air core transformer, and it is

transferred to the secondary side. A rectifier then produces the

isolated power supply, VDDISO. Using another chip scale air

core transformer, a feedback circuit measures VDDISO and

passes the information back into the VDD domain, where a

PWM control block controls the ac source to maintain VDDISO

at 3.3 V.

Figure 47. Isolated DC-to-DC Converter Block Diagram

The PWM control block works at a CLKIN/4 (1.024 MHz)

clock, and every half period generates a PWM pulse to the ac

source (see Figure 48).

Figure 48. PWM Control Block Generates Pulses Based on a 1.024 MHz Clock

Every time a PWM pulse is generated, the ac source transmits

very high frequency signals across the isolation barrier to allow

efficient power transfer through the small chip scale transformers.

This transfer creates high frequency currents that can propagate

in the circuit board ground and power planes, causing edge and

dipole radiation. The Layout Guidelines section describes the

best PCB layout approach to manage the electromagnetic

interference (EMI) issues. In addition to the layout approach,

the 8-bit EMI_CTRL register helps to reduce the emissions

generated by the ADE7912/ADE7913 dc-to-dc converter.

The clock that manages the PWM control block is divided into

eight periodical slots, 0 to 7, as shown in Figure 48. Each bit of

the EMI_CTRL register controls one slot: Bit 0 controls Slot 0,

Bit 1 controls Slot 1, …, Bit 7 controls Slot 7. When the bit is 1,

the default value, the PWM control block generates a pulse.

When the bit is 0, the PWM control block does not generate a

pulse. The recommendation is to have only four of these bits set

to 1 while keeping the others at 0 for every ADE7912/ADE7913

used in the system to further reduce the emissions generated by

the ADE7912/ADE7913 dc-to-dc converter.

If the 3-phase energy meter contains four ADE7912/ADE7913

devices, the ADE7912/ADE7913 devices must first be synchro-

nized (see the Synchronizing Multiple ADE7912/ADE7913

Devices section). Then the EMI_CTRL register of every

ADE7912/ADE7913 must be initialized. The dc-to-dc

converters of only two ADE7912/ADE7913 devices generate

EMI at the same moment, lowering the overall EMI level of the

meter. Initialize the EMI_CTRL register of the Phase A

ADE7912/ADE7913 (EMI_CTRLA) to 0x55, EMI_CTRLB to

0xAA, EMI_CTRLC to 0x55, and EMI_CTRLN to 0xAA (see

Figure 49).

Figure 49. EMI Management of a 3-Phase Meter with Four

ADE7912/ADE7913 Devices

If the system contains one, two, or three ADE7912/ADE7913

devices, set four bits to 1 in the EMI_ CTRL register according

to the approach shown in Figure 49, while leaving some of the

slots unused.

AC SOURCE

ISOLATION

BARRIER

RECTIFIER

VDDISO

FEEDBACK

CIRCUIT

PWM

CONTROL

TO ADC

BLOCK

VDD = 3.3V

PWM CONTROL

PULSE

1.024MHz

CLOCK

ADE7912/ADE7913

PHASE A, PHASE C

PWM PULSE

ADE7912/ADE7913

PHASE B, PHASE N

PWM PULSE

1.024MHz CLOCK

A, C

B, N

A, C

B, N

A, C

B, N

A, C

B, N

A, C

B, N

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