ADE7913 datasheet(29/44 Pages) AD

29 / 44 page

Data Sheet

ADE7912/ADE7913

Rev. 0 | Page 29 of 44

Figure 44. Synchronizing Phase A and Phase B ADE7912/ADE7913 Devices with Phase C ADE7912/ADE7913

Figure 45. CNT_SNAPSHOT Register

The 8-bit SYNC_SNAP register latches the value of the counter

when it is written with 0x02, that is, Bit 1 (snap) set to 1. A

broadcast write to all ADE7912/ADE7913 devices ensures that

all the counters of every ADE7912/ADE7913 are latched at the

same moment. The snap bit clears itself to 0 after one CLKIN

cycle. The values of the counters offer a measure of the ADC

output synchronization across all ADE7912/ADE7913 devices.

Ideally, the values should be perfectly equal, indicating that all

ADE7912/ADE7913 devices are fully synchronized. In reality,

due to the uncertainty between the SPI clock generated by the

microcontroller and the ADE7912/ADE7913 CLKIN, a ±1

count difference between counters is acceptable. The 12-bit

counter is accessed via the 16-bit CNT_SNAPSHOT register

(see Figure 45).

If the internal counter of one ADE7912/ADE7913 device does

not have a value correlated with the values of the counters of the

other ADE7912/ADE7913 devices, this means that the ADC

outputs of one phase are no longer synchronized with the ADC

outputs from the other phases. The ADE7912/ADE7913 provide

two options to resynchronize all the ADE7912/ADE7913

devices: one is to broadcast a write to the 8-bit SYNC_SNAP

ADE7912/ADE7913 devices to start an ADC output cycle

simultaneously. However, all phases present ADC output

distortions of various degrees, a function of when a SYNC_SNAP

= 0x01 write is executed within the current output period.

Therefore, it is recommended that this command be executed at

power-up or after a hardware or software reset.

The other option is to compute a new starting value for the internal

counter of the ADE7912/ADE7913 device that is out of

synchronization. This value forces the internal counter to start a

new ADC output cycle, counting down from it, and end

simultaneously with the other counters of the other ADE7912/

ADE7913 devices. The 12-bit value is stored in two 8-bit

registers, COUNTER1 and COUNTER0 (see Figure 46).

COUNTER0 contains the least significant eight bits and must be

written first. COUNTER1 contains the four most significant bits

and must be written after COUNTER0. The advantage of this

option compared to writing SYNC_SNAP = 0x01 is that only

the ADC outputs of out of sync phases are affected. The other

phases already in synchronization remain unaffected. As a

general rule, it is recommended that the synchronization of the

ADE7912/ ADE7913 devices be verified every couple of

seconds.

Figure 46. Counter Start Value Communicated Using Two 8-Bit Registers

Consider the example shown in Figure 44: the Phase A, Phase B,

and Phase C counters of three ADE7912/ADE7913 devices are

shown for the meter configuration shown in Figure 35. All three

phases are out of synchronization. It is desirable to synchronize

the Phase A and Phase B ADE7912/ADE7913 devices with the

Phase C ADE7912/ADE7913, which is considered the reference

because it generates the DREADY signal.

ADE7912C

ADE7913C

ADE7912B

ADE7913B

ADE7912A

ADE7913A

DREADY

ADC CYCLE 0

ADC CYCLE 1

ADC CYCLE 2

ADC CYCLE 3

ADC CYCLE 4

SYNC_SNAP = 0x02

CA, CB, CC

ARE READ

ALL ADE7912/ADE7913s

ARE IN SYNC

ADE7912B/ADE7913B COUNTER

STARTS FROM A NEW VALUE

ADE7912A/ADE7913A

COUNTER

STARTS FROM A

NEW VALUE

NEW CA = C0 + CC – CA IS WRITTEN (CC < CA)

NEW CB = CC – CB IS WRITTEN (CC > CB)

COUNTER VALUE

0000

8-BIT UNSIGNED

NUMBER

COUNTER[11:0]

COUNTER1[7:0]

COUNTER0[7:0]

0000

4-BIT UNSIGNED

NUMBER

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