ADE7913 datasheet(18/44 Pages) AD

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ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 18 of 44

THEORY OF OPERATION

ANALOG INPUTS

The ADE7913 has three analog inputs: one current channel and

two voltage channels. The ADE7912 does not include the

second voltage channel. The current channel has two fully

differential voltage input pins, IP and IM, that accept a maxi-

mum differential signal of ±31.25 mV.

The maximum VIP signal level is also ±31.25 mV. The maxi-

mum VIM signal level allowed at the IM input is ±25 mV.

Figure 23 shows a schematic of the input for the current channel

and its relation to the maximum IM pin voltage.

Figure 23. Maximum Input Level, Current Channel

Note that the current channel is used to sense the voltage across

a shunt. In this case, one pole of the shunt becomes the ground

of the meter (see Figure 33) and, therefore, the current channel

is used in a pseudo differential configuration, similar to the

voltage channel configuration (see Figure 24).

The voltage channel has two pseudo differential, single-ended

voltage input pins: V1P and V2P. These single-ended voltage

inputs have a maximum input voltage of ±500 mV with respect

to VM. The maximum signal allowed at the VM input is

±25 mV. Figure 24 shows a schematic of the voltage channel

inputs and their relation to the maximum VM voltage.

Figure 24. Maximum Input Level, Voltage Channels

ANALOG-TO-DIGITAL CONVERSION

The ADE7912/ADE7913 have three second-order Σ-Δ ADCs.

For simplicity, the block diagram in Figure 25 shows a first-order

Σ-Δ ADC. The converter is composed of the Σ-Δ modulator

and the digital low-pass filter, separated by the digital isolation

block.

Figure 25. First-Order Σ-Δ ADC

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7912/ADE7913, the sampling clock is equal to

CLKIN/4 (1.024 MHz when CLKIN = 4.096 MHz). The 1-bit

DAC in the feedback loop is driven by the serial stream. The

DAC output is subtracted from the input signal. If the loop gain

is high enough, the average value of the DAC output (and,

therefore, the bit stream) can approach that of the input signal

level. For any given input value in a single sampling interval, the

data from the 1-bit ADC is virtually meaningless. A meaningful

result is obtained only when a large number of samples is

averaged. This averaging is completed in the second part of the

ADC, the digital low-pass filter, after the data is passed through

the digital isolators. By averaging a large number of bits from

the modulator, the low-pass filter can produce 24-bit data-

words that are proportional to the input signal level.

The Σ-Δ converter uses two techniques to achieve high resolu-

tion from what is essentially a 1-bit conversion technique. The

first technique is oversampling. Oversampling means that the

signal is sampled at a rate (frequency) that is many times higher

than the bandwidth of interest. For example, when CLKIN =

4.096 MHz, the sampling rate in the ADE7912/ADE7913 is

1.024 MHz, and the bandwidth of interest is 40 Hz to 3.3 kHz.

Oversampling has the effect of spreading the quantization noise

(noise due to sampling) over a wider bandwidth. With the noise

spread more thinly over a wider bandwidth, the quantization

noise in the bandwidth of interest is lowered, as shown in

Figure 26.

However, oversampling alone is not sufficient to improve the

signal-to-noise ratio (SNR) in the band of interest. For example, an

oversampling factor of 4 is required to increase the SNR by a

mere 6 dB (1 bit). To keep the oversampling ratio at a

reasonable level, it is possible to shape the quantization noise so

that the majority of the noise lies at the higher frequencies.

Noise shaping is the second technique used to achieve high

resolution. In the Σ-Δ modulator, the noise is shaped by the

integrator, which has a high-pass type response for the

quantization noise. The result is that most of the noise is at the

higher frequencies where it can be removed by the digital low-

pass filter. This noise shaping is shown in Figure 26.

VIM

VIP

+31.25mV

VIP

VIP = ±31.25mV MAX PEAK

VIM = ±25mV MAX

–31.25mV

V1P OR

V2P

+500mV

V1 = ±500mV MAX PEAK

VM = ±25mV MAX

–500mV

DIGITAL

LOW-PASS

FILTER

–

CLKIN/16

INTEGRATOR

VREF

1-BIT DAC

LATCHED

COMPARATOR

ANALOG

LOW-PASS

FILTER

.....10100101.....

–

DIGITAL

ISOLATION

BARRIER

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