ADE7913 datasheet(26/44 Pages) AD

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ADE7912/ADE7913

Data Sheet

Rev. 0 | Page 26 of 44

SPI-COMPATIBLE INTERFACE

The SPI of the ADE7912/ADE7913 is the slave of the

communication and consists of four pins: SCLK, MOSI, MISO,

and CS. The serial clock for a data transfer is applied at the

SCLK logic input. All data transfer operations synchronize

to the serial clock. Data shifts into the ADE7912/ADE7913 at

the MOSI logic input on the falling edge of SCLK, and the

ADE7912/ADE7913 sample the data on the rising edge of

SCLK. Data shifts out of the ADE7912/ADE7913 at the MISO

logic output on the falling edge of SCLK and can be sampled

by the master device on the rising edge of SCLK. The most

significant bit of the word is shifted in and out first. The

maximum and minimum serial clock frequencies supported by

this interface are 5.6 MHz and 250 kHz, respectively. MISO

stays in high impedance when no data is transmitted from the

ADE7912/ADE7913. At power-up or during hardware or

software reset, the microcontroller reads the STATUS0 register

to detect when Bit 0 (RESET_ON) clears to 0. See Figure 39

for details of the connections between the SPI ports of three

ADE7912/ADE7913 devices and a microcontroller containing

an SPI interface.

The CS logic input is the chip select input. Drive the CS input

low for the entire data transfer operation. Bringing CS high

during a data transfer operation leaves the ADE7912/ADE7913

aborts the transfer and places the serial bus in a high impedance

state. A new transfer can then be initiated by returning the CS

logic input to low.

Figure 41. SPI Read Operation of an 8-Bit Register

Figure 42. SPI Read Operation in Burst Mode

Figure 43. SPI Write Operation

SCLK

MOSI

MISO

ADDR[4:0]

SCLK

MOSI

MISO

IWV

CNT_SNAPSHOT

SCLK

MOSI

0 0

ADDR[4:0]

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