ADE7913 datasheet(37/44 Pages) AD

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Data Sheet

ADE7912/ADE7913

Rev. 0 | Page 37 of 44

LAYOUT GUIDELINES

Figure 20 shows the test circuit of the ADE7912/ADE7913. The

test circuit contains three ADE7912/ADE7913 devices together

with the surrounding circuitry required to sense the phase

currents and voltages in a 3-phase system. The ADE7912/

ADE7913 devices are managed by a microcontroller using the

SPI interface. The microcontroller is not shown in the

schematic. Figure 20 replicates the schematic of the ADE7913

evaluation board (see the ADE7913 Evaluation Board section).

Figure 55 and Figure 56 show a proposed layout of a printed

circuit board (PCB) with two layers that have the components

placed on the top of the board only. Follow these layout

guidelines to create a low noise design with higher immunity to

EMC influences. Note that the layout is cropped from a board

containing other circuitry besides the three ADE7913 devices.

The layout of an ADE7912-based meter is very similar to the

one designed for the ADE7913. The only difference is the

absence of the V2P voltage channel, which means the absence

of the related circuitry: the resistor divider and the protection

diodes.

The primary supply voltage is supplied at VDD, Pin 19. Place a

10 µF decoupling capacitor and a 100 nF ceramic decoupling

capacitor between the VDD pin and GND, Pin 20. The 10 µF

capacitor must be placed in close proximity to the part, but the

ceramic capacitor must be placed closer to the ADE7912/

ADE7913 because it decouples the high frequency noise.

Use a 10 µF capacitor and a 100 nF ceramic capacitor to

decouple VDDISO, Pin 1, from GNDISO, Pin 2. Apply the same

rules in the placement of these capacitors as for the VDD pin.

Use a 4.7 µF capacitor and a 100 nF, ceramic capacitor to

decouple LDO, Pin 8, and REF, Pin 9, from GNDISO, Pin 10.

Use the same rules in the placement of these capacitors as for

the VDD pin.

Note that the ADE7912/ADE7913 isolated ground point is one

of the shunt poles. This point is directly connected to GNDISO,

Pin 10. There is no need to connect the shunt ground pole to

GNDISO, Pin 2. Pin 2 is internally connected to Pin 10.

The crystal load capacitors must be placed closest to the

ADE7912/ADE7913, whereas the crystal can be placed in close

proximity.

Note that the bottom layer extends the ground of the primary

side below the ADE7912/ADE7913 and the related circuitry. A

distance of at least 8 mm is maintained on the bottom layer

between the input pins on the board and the primary side

ground plane.

Figure 55. 2-Layer Circuit Board: Top Layer

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