数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

TAS5731MPHPR 数据表(PDF) 27 Page - Texas Instruments

Click here to check the latest version.
部件名 TAS5731MPHPR
功能描述  2 * 30-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TAS5731MPHPR 数据表(HTML) 27 Page - Texas Instruments

Back Button TAS5731MPHPR Datasheet HTML 23Page - Texas Instruments TAS5731MPHPR Datasheet HTML 24Page - Texas Instruments TAS5731MPHPR Datasheet HTML 25Page - Texas Instruments TAS5731MPHPR Datasheet HTML 26Page - Texas Instruments TAS5731MPHPR Datasheet HTML 27Page - Texas Instruments TAS5731MPHPR Datasheet HTML 28Page - Texas Instruments TAS5731MPHPR Datasheet HTML 29Page - Texas Instruments TAS5731MPHPR Datasheet HTML 30Page - Texas Instruments TAS5731MPHPR Datasheet HTML 31Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 27 / 68 page
background image
23
22
SCLK
32Clks
LRCLK(NoteReversedPhase)
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
32Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0034-01
5
4
9
8
1
0
0
4
5
1
0
23
22
1
19
18
15
14
MSB
LSB
5
4
9
8
1
0
0
4
5
1
0
SCLK
TAS5731M
www.ti.com
SLOS838B – JULY 2013 – REVISED NOVEMBER 2013
PWM SECTION
The TAS5731M DAP device uses noise-shaping and customized nonlinear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual-channel dc-blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can
be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For a detailed description of using audio processing features like DRC and EQ, see the User's Guide and
TAS570X GDE software development tool documentation.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 46. I2S 64-fS Format
Copyright © 2013, Texas Instruments Incorporated
27
Product Folder Links :TAS5731M



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com