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TAS5731MPHPR 数据表(PDF) 7 Page - Texas Instruments |
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TAS5731MPHPR 数据表(HTML) 7 Page - Texas Instruments |
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7 / 68 page  TAS5731M www.ti.com SLOS838B – JULY 2013 – REVISED NOVEMBER 2013 PIN FUNCTIONS (continued) PIN 5-V TYPE(1) TERMINATION(2) DESCRIPTION TOLERANT NAME NO. AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 4 P High-side bootstrap supply for half-bridge A BST_B 43 P High-side bootstrap supply for half-bridge B BST_C 42 P High-side bootstrap supply for half-bridge C BST_D 33 P High-side bootstrap supply for half-bridge D DVDD 27 P 3.3-V digital power supply DVSS 28 P Digital ground DVSSO 17 P Oscillator ground GND 29 P Analog ground for power stage GVDD_OUT 32 P Gate drive internal regulator output LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample-rate clock) MCLK 15 DI 5-V Pulldown Master clock input NC 5, 7, – No connect 40, 41, 44, 45 OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-k Ω, 1% resistor to DVSSO. OUT_A 1 O Output, half-bridge A OUT_B 46 O Output, half-bridge B OUT_C 39 O Output, half-bridge C OUT_D 36 O Output, half-bridge D PBTL 8 DI Pulldown Low means BTL mode; high means PBTL mode. Information goes directly to power stage. PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power supplies by shutting down the noise shaper and initiating the PWM stop sequence. PGND_AB 47, 48 P Power ground for half-bridges A and B PGND_CD 37, 38 P Power ground for half-bridges C and D PLL_FLTM 10 AO PLL negative loop-filter terminal PLL_FLTP 11 AO PLL positive loop-filter terminal PVDD_AB 2, 3 P Power-supply input for half-bridge output A and B PVDD_CD 34, 35 P Power-supply input for half-bridge output C and D RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET is an asynchronous control signal that restores the DAP to its default conditions and places the PWM in the hard-mute (high-impedance) state. SCL 24 DI 5-V I2C serial control clock input SCLK 21 DI 5-V Pulldown Serial audio-data clock (shift clock). SCLK is the serial-audio-port input-data bit clock. SDA 23 DIO 5-V I2C serial control data interface input/output SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data formats. SSTIMER 6 AI Controls ramp time of OUT_x to minimize pop. Leave this pin floating for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp time. STEST 26 DI Factory test pin. Connect directly to DVSS. VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be used to power external devices. VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be used to power external devices. Copyright © 2013, Texas Instruments Incorporated 7 Product Folder Links :TAS5731M |
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