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TAS5731MPHPR 数据表(PDF) 28 Page - Texas Instruments

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部件名 TAS5731MPHPR
功能描述  2 * 30-W DIGITAL AUDIO POWER AMPLIFIER WITH DSP AND 2.1 MODE
PDF  68 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TAS5731MPHPR 数据表(HTML) 28 Page - Texas Instruments

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SCLK
16Clks
LRCLK
LeftChannel
16-BitMode
1
1
15
15
14
14
MSB
LSB
16Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput
2
T0266-01
3
3
2
2
5
5
4
4
9
9
8
8
0
13
13
10
10
11
11
12
12
SCLK
MSB
LSB
23
22
SCLK
24Clks
LRCLK
LeftChannel
24-BitMode
1
19
18
20-BitMode
16-BitMode
15
14
MSB
LSB
24Clks
RightChannel
2-ChannelI S(PhilipsFormat)StereoInput/Output(24-Bit TransferWordSize)
2
T0092-01
3
2
5
4
9
8
17
16
1
0
0
4
5
13
12
1
0
9
8
23
22
SCLK
1
19
18
15
14
MSB
LSB
3
2
5
4
9
8
17
16
1
0
4
5
13
12
1
0
9
8
TAS5731M
SLOS838B – JULY 2013 – REVISED NOVEMBER 2013
www.ti.com
NOTE: All data presented in 2s-complement form with MSB first.
Figure 47. I2S 48-fS Format
NOTE: All data presented in 2s-complement form with MSB first.
Figure 48. I2S 32-fS Format
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
28
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links :TAS5731M



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