TAS5731MPHPR datasheet(32/68 Pages) TI1

32 / 68 page

7-BitSlave Address

8-BitRegister Address(N)

8-BitRegisterDataFor

Address(N)

Start

Stop

SDA

SCL

8-BitRegisterDataFor

Address(N)

T0035-01

TAS5731M

SLOS838B – JULY 2013 – REVISED NOVEMBER 2013

www.ti.com

2C SERIAL CONTROL INTERFACE

The TAS5731M DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and

supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations.

This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The

control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation

(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.

General I2C Operation

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a

system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte

(8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is

acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master

device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.

The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A

high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit

transitions must occur within the low time of the clock period. These conditions are shown in Figure 55. The

master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another

device and then waits for an acknowledge condition. The TAS5731M holds SDA low during the acknowledge

clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the

sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible

devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor

must be used for the SDA and SCL signals to set the high level for the bus.

Figure 55. Typical I2C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last

word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is

shown in Figure 55.

The 7-bit address for TAS5731M is 0011 011 (0x36).

Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses

0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-

byte read/write operations (in multiples of 4 bytes).

During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress

assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does

not contain 32 bits, the unused bits are read as logic 0.

During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes

that are required for each specific subaddress. For example, if a write command is received for a biquad

subaddress, the DAP must receive five 32-bit words. If fewer than five 32-bit data words have been received

when a stop command (or another start command) is received, the received data is discarded.

Product Folder Links :TAS5731M

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