AGLP030 datasheet(127/134 Pages) MICROSEMI

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Revision 16

5-1

5 – Datasheet Information

List of Changes

The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet.

Revision

Changes

Page

Revision 16

(December 2012)

The "IGLOO PLUS Ordering Information" section has been updated to mention "Y"

as "Blank" mentioning "Device Does Not Include License to Implement IP Based on

the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175).

III

The note in Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 •

IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised

to refer instead to the online help associated with the core (SAR 42566).

2-61,

2-62

Live at Power-Up (LAPU) has been replaced with ’Instant On’.

Revision 15

(October 2012)

Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in

Table 2-15 • Different Components Contributing to Dynamic Power Consumption in

IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage

in Table 2-17 • Different Components Contributing to Dynamic Power Consumption

in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables.

2-10,

2-11

Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip

(SoC) throughout the document (SAR 40277).

N/A

Revision 14

(September 2012)

The "Security" section was modified to clarify that Microsemi does not support read-

back of programmed data.

1-2

Revision 13

(June 2012)

Figure 2-30 • FIFO Read and Figure 2-31 • FIFO Write have been added (SAR

34843).

2-73

Updated the terminology used in Timing Characteristics in the following tables:

Table 2-96 • FIFO and Table 2-97 • FIFO (SAR 38236).

2-76

The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"

section in the "Pin Descriptions and Packaging" section: "Within the package, the

VMV plane is decoupled from the simultaneous switching noise originating from the

output buffer VCCI domain" and replaced with “Within the package, the VMV plane

biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet

mentions that "VMV pins must be connected to the corresponding VCCI pins" for an

ESD enhancement.

3-1

Revision 12

(March 2012)

The "In-System Programming (ISP) and Security" section and "Security" section

were revised to clarify that although no existing security measures can give an

absolute guarantee, Microsemi FPGAs implement the best security available in the

industry (SAR 34664).

I, 1-2

The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS

Ordering Information" section. The trademarked Licensed DPA Logo identifies that a

product is covered by a DPA counter-measures license from Cryptography Research

(SAR 34724).

III

The "Specifying I/O States During Programming" section is new (SAR 34695).

1-7

The following sentence was removed from the "Advanced Architecture" section:

"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage

(3.3 V) programming of IGLOO PLUS devices via an IEEE 1532 JTAG interface"

(SAR 34684).

1-3

AGLP030 数据表(PDF) 127 Page - Microsemi Corporation

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