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数据搜索系统，热门电子元器件搜索 |
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AX2000 数据表(PDF) 117 Page - Microsemi Corporation |
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AX2000 数据表(HTML) 117 Page - Microsemi Corporation |
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117 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 103 Table 2-99 • Two FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Units Parameter Description Min. Max. Min. Max. Min. Max. FIFO Module Timing tWSU Write Setup 13.75 15.66 18.41 ns tWHD Write Hold 0.00 0.00 0.00 ns tWCKH WCLK High 0.75 0.75 0.75 ns tWCKL WCLK Low 1.76 1.76 1.76 ns tWCKP Minimum WCLK Period 2.51 2.51 2.51 ns tRSU Read Setup 14.33 16.32 19.19 ns tRHD Read Hold 0.00 0.00 0.00 ns tRCKH RCLK High 0.73 0.73 0.73 ns tRCKL RCLK Low 1.89 1.89 1.89 ns tRCKP Minimum RCLK period 2.62 2.62 2.62 ns tCLRHF Clear High 0.00 0.00 0.00 ns tCLR2FF Clear-to-flag (EMPTY/FULL) 1.92 2.18 2.57 ns tCLR2AF Clear-to-flag (AEMPTY/AFULL) 4.39 5.00 5.88 ns tCK2FF Clock-to-flag (EMPTY/FULL) 2.13 2.42 2.85 ns tCK2AF Clock-to-flag (AEMPTY/AFULL) 5.04 5.75 6.75 ns tRCK2RD1 RCLK-To-OUT (Pipelined) 1.43 1.63 1.92 ns tRCK2RD2 RCLK-To-OUT (Nonpipelined) 2.26 2.58 3.03 ns Note: Timing data for these two cascaded FIFO blocks uses a depth of 8,192. For all other combinations, use Microsemi’s timing software. |
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