AX2000 datasheet(121/262 Pages) MICROSEMI

121 / 262 page

Axcelerator Family FPGAs

Re vi s i on 18

2 - 107

mode if desired. Please note, if the I/O bank is not disabled, differential I/Os belonging to the I/O bank will

still consume normal power, even when operating in the low power mode.

The Axcelerator device will resume normal operation 10

μs after the LP pin is pulled Low.

To further reduce power consumption, the internal charge pump can be bypassed and an external power

supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in

no DC current draw. The Axcelerator family devices have a dedicated "VPUMP" pin that can be used to

access an external charge pump device. In normal chip operation, when using the internal charge pump,

VPUMP should be tied to GND. When the voltage level on VPUMP is set to 3.3V, the internal charge pump

is turned off, and the VPUMP voltage will be used as the charge pump voltage. Adequate voltage

regulation (i.e. high drive, low output impedance, and good decoupling) should be used at VPUMP.

In addition, any PLL in use can be powered down to further reduce power consumption. This can be

done with the PowerDown pin driven Low. Driving this pin High restarts the PLL with the output clock(s)

being stable once lock is restored.

JTAG

Axcelerator offers a JTAG interface that is compliant with the IEEE 1149.1 standard. The user can

employ the JTAG interface for probing a design and performing any JTAG Public Instructions as defined

in the Table 2-103.

Interface

The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP

Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up

resistors.

TRST

TRST (Test-Logic Reset) is an active-low, asynchronous reset signal to the TAP controller. The TRST

input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller

can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the

TRST state, it is recommended to connect TRST to ground via a 1 k

Ω resistor.

There is an optional internal pull-up resistor available for the TRST input that can be set by the user at

programming. Care should be exercised when using this option in combination with an external tie-off to

ground.

An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST,"

but it only occurs at power-up or during recovery from a VCCA and/or VCCDA voltage drop.

Table 2-103 • JTAG Instruction Code

Instruction (IR4:IR0)

Binary Code

Extest

00000

Preload / Sample

00001

Intest

00010

USERCODE

00011

IDCODE

00100

HIGHZ

01110

CLAMP

01111

Diagnostic

10000

Reserved

All others

Bypass

11111

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