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MPC8347ECVRADDB 数据表(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC8347ECVRADDB 数据表(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 24 Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management 8.1.1 TSEC DC Electrical Characteristics GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 23 and Table 24. The RGMII and RTBI signals in Table 24 are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5. 8.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section. 8.2.1 GMII Timing Specifications This section describes the GMII transmit and receive AC timing specifications. Table 23. GMII/TBI and MII DC Electrical Characteristics Parameter Symbol Conditions Min Max Unit Supply voltage 3.3 V LVDD 2 — 2.97 3.63 V Output high voltage VOH IOH = –4.0 mA LVDD = Min 2.40 LVDD +0.3 V Output low voltage VOL IOL = 4.0 mA LVDD = Min GND 0.50 V Input high voltage VIH —— 2.0 LVDD +0.3 V Input low voltage VIL — — –0.3 0.90 V Input high current IIH VIN 1 = LV DD —40 μA Input low current IIL VIN 1 = GND –600 — μA Notes: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply. Table 24. RGMII/RTBI (When Operating at 2.5 V) DC Electrical Characteristics Parameters Symbol Conditions Min Max Unit Supply voltage 2.5 V LVDD — 2.37 2.63 V Output high voltage VOH IOH = –1.0 mA LVDD = Min 2.00 LVDD +0.3 V Output low voltage VOL IOL = 1.0 mA LVDD = Min GND – 0.3 0.40 V Input high voltage VIH —LVDD = Min 1.7 LVDD +0.3 V Input low voltage VIL —LVDD = Min –0.3 0.70 V Input high current IIH VIN 1 = LV DD —10 μA Input low current IIL VIN 1 = GND –15 — μA Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. |
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