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MPC8347ECVRADDB 数据表(PDF) 81 Page - Freescale Semiconductor, Inc

部件名 MPC8347ECVRADDB
功能描述  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications
PDF  99 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8347ECVRADDB 数据表(HTML) 81 Page - Freescale Semiconductor, Inc

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
Freescale Semiconductor
81
Clocking
19.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300
core clock (core_clk). Table 63 shows the encodings for RCWL[COREPLL]. COREPLL values that are
not listed in Table 63 should be considered as reserved.
NOTE
Core VCO frequency = core frequency
× VCO divider
Table 62. CSB Frequency Options for Agent Mode
CFG_CLKIN_DIV
at Reset1
1 CFG_CLKIN_DIV doubles csb_clk if set high.
SPMF
csb_clk :
Input Clock Ratio2
2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
DDR2 memory may be used at 133 MHz provided that the memory components are specified for operation at this frequency.
Input Clock Frequency (MHz)2
16.67
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2 : 1
133
Low
0011
3 : 1
100
200
Low
0100
4 : 1
100
133
266
Low
0101
5 : 1
125
166
333
Low
0110
6 : 1
100
150
200
Low
0111
7 : 1
116
175
233
Low
1000
8 : 1
133
200
266
Low
1001
9 : 1
150
225
300
Low
1010
10 : 1
166
250
333
Low
1011
11 : 1
183
275
Low
1100
12 : 1
200
300
Low
1101
13 : 1
216
325
Low
1110
14 : 1
233
Low
1111
15 : 1
250
Low
0000
16 : 1
266
High
0010
4 : 1
100
133
266
High
0011
6 : 1
100
150
200
High
0100
8 : 1
133
200
266
High
0101
10 : 1
166
250
333
High
0110
12 : 1
200
300
High
0111
14 : 1
233
High
1000
16 : 1
266



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