MPC8347ECVRADDB datasheet(15/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

RESET Initialization

5.2

RESET AC Electrical Characteristics

Table 10 provides the reset initialization AC timing specifications of the MPC8347EA.

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.

2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.

Table 10. RESET Initialization Timing Specifications

Parameter

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN when the

MPC8347EA is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN

when the MPC8347EA is in PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is

in PCI host mode

4—

tCLKIN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is

in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR configuration signals with respect to negation of HRESET

0—

—

Time for the MPC8347EA to turn off POR configuration signals with respect to the

assertion of HRESET

—4

Time for the MPC8347EA to turn on POR configuration signals with respect to the

negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied

to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA

PowerQUICC II Pro Integrated Host Processor Family Reference Manual.

3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 9. RESET Pins DC Electrical Characteristics1 (continued)

Parameter

Symbol

Condition

Min

Max

Unit

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