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MPC8347ECVRADDB 数据表(PDF) 83 Page - Freescale Semiconductor, Inc |
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MPC8347ECVRADDB 数据表(HTML) 83 Page - Freescale Semiconductor, Inc |
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83 / 99 page  MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12 Freescale Semiconductor 83 Clocking 19.3 Suggested PLL Configurations Table 64 shows suggested PLL configurations for 33 and 66 MHz input clocks. Table 64. Suggested PLL Configurations Ref No.1 RCWL 400 MHz Device 533 MHz Device 667 MHz Device SPMF CORE PLL Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) Input Clock Freq (MHz)2 CSB Freq (MHz) Core Freq (MHz) 33 MHz CLKIN/PCI_CLK Options 922 1001 0100010 ————— f300 33 300 300 723 0111 0100011 33 233 350 33 233 350 33 233 350 604 0110 0000100 33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100011 33 266 400 33 266 400 33 266 400 903 1001 0000011 — 33300 45033300 450 923 1001 0100011 — 33300 45033300 450 704 0111 0000011 — 33233 46633233 466 724 0111 0100011 — 33233 46633233 466 A03 1010 0000011 — 33 333 500 33 333 500 804 1000 0000100 — 33266 53333266 533 705 0111 0000101 — — 33 233 583 606 0110 0000110 — — 33 200 600 904 1001 0000100 — — 33 300 600 805 1000 0000101 — — 33 266 667 A04 1010 0000100 — — 33 333 667 66 MHz CLKIN/PCI_CLK Options 304 0011 0000100 66 200 400 66 200 400 66 200 400 324 0011 0100100 66 200 400 66 200 400 66 200 400 403 0100 0000011 66 266 400 66 266 400 66 266 400 423 0100 0100011 66 266 400 66 266 400 66 266 400 305 0011 0000101 — 66200 50066200 500 503 0101 0000011 — 66 333 500 66 333 500 404 0100 0000100 — 66266 53366266 533 |
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