CS494502 datasheet(59/100 Pages) CIRRUS

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6.3.5 Intel Parallel Host Communication

Mode for DSPC

The Intel parallel host communication mode is

implemented using the pins given in Table 9.

Parallel host communication is available only on

the 144-pin package version of the CS49400.

The INTREQ pin is asserted (driven low)

whenever the DSP has an outgoing message for the

host. This same information is reflected by the

HOUTRDY bit of the Host Control Register

(A[1:0] = 01b).

INTREQ is useful for informing the host of

unsolicited messages. An unsolicited message is

defined as a message generated by the DSP without

an associated host read request.

6.3.5.1 Writing a Byte in Intel Mode for DSPC

Information provided in this section is intended as

a functional description of how to write control

information to DSPC. The system designer must

ensure that all of the timing constraints of the Intel

Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 42 illustrates

the sequence of events that define a one-byte write

in Intel mode. One-byte writes should only be

perfomed to the Host Control and Host Data

registers. The protocol presented in Figure 42 will

now be described in detail.

1) The host must first drive the A1 and A0 register

address pins of DSPC with the address of the

desired Parallel I/O Register. The address is

latched on the falling edge of CS.

Host Control:

A[1:0]==01b.

Host Data1:

A[1:0]==10b.

Host Data2:

A[1:0]==11b.

2) The host initiates a write cycle by driving the

CS and WR pins low.

3) The host drives the data byte to the HDAT[7:0]

pins of DSPC.

4) Once the setup time for the write has been met,

the host ends the write cycle by driving the WR

and CS pins high.

Mnemonic

Pin Name

144-Pin

Package,

Number

Chip Select

129

Write Enable

120

Output Enable

121

139

130

Interrupt Request

INTREQ

Host Busy

HINBSY

141

DATA7

HDAT7

DATA6

HDAT6

DATA5

HDAT5

DATA4

HDAT4

103

DATA3

HDAT3

105

DATA2

HDAT2

112

DATA1

HDAT1

115

DATA0

HDAT0

116

Table 9. Intel Mode Communication Signals for DSPC

CS (HIGH)

WR (HIGH)

W RITEBYTETO

HDAT[7:0]

CS (LOW )

WR (LOW )

ADDRESS A PARALLEL I/O REGISTER

(A[1:0] SET APPROPRIATELY)

Figure 42. Intel Mode, One-Byte Write Flow Diagram

for DSPC

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