CS494502 datasheet(5/100 Pages) CIRRUS

5 / 100 page

Figure 42. Intel Mode, One-Byte Write Flow Diagram for DSPC .......................................................60

Figure 44. Intel Mode, One-Byte Read Flow Diagram for DSPC ......................................................61

Figure 43. Intel Mode, 32-bit (4-byte) Write Flow

Diagram for DSPC .............................................................................................................................62

Figure 45. Intel Mode, 32-Bit (4-Byte) Read Flow

Diagram for DSPC .............................................................................................................................63

Figure 46. Motorola Mode, One-Byte Write Flow

Diagram for DSPC .............................................................................................................................64

Figure 47. Motorola Mode, 32-bit (4-byte) Write Flow Diagram for DSPC ........................................65

Figure 48. Motorola Mode, One-Byte Read Flow

Diagram for DSPC .............................................................................................................................66

Figure 49. Motorola Mode, 32-Bit (4-Byte) Read Flow Diagram for DSPC .......................................67

Figure 50. Typical Parallel Host Mode Control Write Sequence Flow Diagram for DSPC ................68

Figure 51. Typical Parallel Host Mode Control Read Sequence Flow Diagram for DSPC ................69

Figure 52. Host Controlled Master Boot

(Downloading both a DSPAB Application Code and a DSPC Application Code) ..............................73

Figure 53. Host Boot Via DSPC .......................................................................................................76

Figure 54. Host Controlled Master Softreset .....................................................................................78

Figure 55. I2S Format ........................................................................................................................80

Figure 56. Left Justified Format (Rising Edge Valid SCLK) ...............................................................80

Figure 57. Pin Layout (144-Pin LQFP Package) ...............................................................................87

Figure 58. Pin Layout (100-Pin LQFP Package) ...............................................................................88

Figure 59. 144-Pin LQFP Package Drawing ...................................................................................100

CS494502 数据表(PDF) 5 Page - Cirrus Logic