CS494502 datasheet(12/100 Pages) CIRRUS

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1.9 Switching Characteristics — Intel® Host Slave Mode (DSPC)

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =

1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns

DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

Parameter

Symbol

Min

Max

Unit

Address setup before CS and RD low or CS and WR low

Tias

DCLKP

Address hold time after CS and RD low or CS and WR low

Tiah

DCLKP+15

Read

Delay between RD then CS low or CS then RD low

Ticdr

Data valid after CS and RD low

Tidd

2*DCLKP+

CS and RD low for read

(Note 1)

Tirpw

2*DCLKP

Data hold time after CS or RD high

Tidhr

DCLKP+10

Data high-Z after CS or RD high

Tidis

2*DCLKP+

CS or RD high to CS and RD low for next read

(Note 1)

Tird

2*DCLKP+10

CS or RD high to CS and WR low for next write

(Note 1)

Tirdtw

2*DCLKP+10

Write

Delay between WR then CS low or CS then WR low

Ticdw

Data setup before CS or WR high

Tidsu

2*DCLKP+10

CS and WR low for write

(Note 1)

Tiwpw

2*DCLKP

Data hold after CS or WR high

Tidhw

DCLKP

CS or WR high to CS and RD low for next read

(Note 1)

Tiwtrd

2*DCLKP+10

CS or WR high to CS and WR low for next write

(Note 1)

Tiwd

2*DCLKP+10

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