CS494502 datasheet(83/100 Pages) CIRRUS

83 / 100 page

MCLK

input. All consumer channel status

information can be included in the S/PDIF stream,

provided that the particular application code

supports this functionality.

When configured as a S/PDIF transmitter, the

designer should understand that in order for these

ports to be fully IEC60958 compliant, the outputs

would need to be buffered through an RS422

device or an optocoupler as its outputs are only

CMOS driven.

11.7 Output Data Hardware Configuration

The DAO naming convention is as follows:

OUTPUT ABCD,

where the parameters are defined as:

A - DAO Mode (Master/Slave for LRCLK0,

LRCLK1, SCLK0 and SCLK1)

B- Data Format

C - MCLK, SCLK, LRCLK Frequency

The following tables show the different values for

each parameter as well as the hex message that

needs to be sent. When creating the hardware

configuration message, only one hex message

should be sent per parameter.

Value

DAO Modes (LRCLK and

SCLK)

Hex Message

(default)

MCLK - Slave

SCLK0 - Slave

LRCLK0 - Slave

SCLK1 - Slave

LRCLK1 - Slave

0x81800003

0x00101000

1MCLK - Slave

SCLK0 - Master

LRCLK0 - Master

SCLK1 - Master

LRCLK1 - Master

0x81800003

0xFFEFFFFF

Table 27. Output Clock Configuration

(Parameter A)

Value

DAO Data Format Of

AUDATA0, 1, 2 (or

AUDATA0 for Multichannel

Modes)

Hex

Message

(default)

I2S 24-bit

(Configuration of AUDATA3 as

S/PDIF (IEC60958) or Digital Audio

in the format of I

2S or Left Justified is

coveredinAN209)

0x81800003

0xFFFE3FFF

0x81400003

0x0001C000

0x81000005

0x00101701

0x81000006

0x00100001

0x81000007

0x00100001

0x81000008

0x00100001

Left Justified 24-bit

(Configuration of AUDATA3 as

S/PDIF (IEC60958) or Digital Audio

in the format of I

2S or Left Justified is

coveredinAN209)

0x81800003

0xFFFE3FFF

0x81400003

0x0000C000

0x81000005

0x00101701

0x81000006

0x00100000

0x81000007

0x00100000

0x81000008

0x00100000

Table 28. Output Data Configuration Parameter B)

C Value

SCLK/LRCLK Frequency

Hex

Message

(default)

MCLK = 256 FS

SCLK = MCLK / 4 = 64 FS

LRCLK = SCLK / 64 = FS

0x81800003

0xFFFFFC7F

0x81400003

0x00000100

0x81000009

0x00077030

MCLK = 256 FS

SCLK = MCLK / 2 = 128 FS

LRCLK = SCLK / 128 = FS

0x81800003

0xFFFFFC7F

0x81400003

0x00000200

0x81000009

0x00177010

Table 29. Output SCLK/LRCLK Configuration

(Parameter C)

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