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CS494502 数据表(PDF) 20 Page - Cirrus Logic

部件名 CS494502
功能描述  Multi-Standard Audio Decoder Family
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS494502 数据表(HTML) 20 Page - Cirrus Logic

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1.13 Switching Characteristics — SPI Control Port Slave Mode (DSPC)
(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)
Notes: 1. The specification fsck indicates the maximum speed of the hardware. The system designer should be
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
2. Data must be held for sufficient time to bridge the transition time of SCCLK.
Parameter
Symbol
Min
Max
Units
SCCLK clock frequency
(Note 1)
fsck
-5
MHz
CS falling to SCCLK rising
tcss
4*DCLKP
-
ns
SCCLK low time
tscl
4*DCLKP
-
ns
SCCLK high time
tsch
4*DCLKP
-
ns
Setup time SCDIN to SCCLK rising
tcdisu
DCLKP
-
ns
Hold time SCCLK rising to SCDIN
(Note 2)
tcdih
DCLKP+20
-
ns
Time from SCCLK low to SCDOUT valid
tscdov
-
3*DCLKP+20
ns
Time from SCCLK rising to INTREQ rising
tscrh
-
DCLKP
ns
Hold time for INTREQ from SCCLK rising
tscrl
DCLKP
-
ns
Time from SCCLK falling to CS rising
tsccsh
2*DCLKP+15
-
ns
Time from SCCLK low to CS falling
tsccsl
10
ns
High time between active CS
tcsht
4*DCLKP
-
ns
Time from CS rising to SCDOUT high-Z
tcscdo
DCLKP
ns



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