CS494502 datasheet(69/100 Pages) CIRRUS

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HOUTRDY bit (return to step 1).

6) After the response has been read the host

should wait at least 100 uS and check

HOUTRDY one final time. If HOUTRDY is

high once again this means that an unsolicited

message has come during the read process and

the host has another message to read (i.e. skip

back to step 4 and read out the new message). It

is the host’s responsibility to insure that any

pending messages are read from the DSP.

Failure to do this may cause the DSP’s output

message buffer to overflow, corrupting any

pending outbound messages.

7. EXTERNAL MEMORY

The system designer has the option of using

external memory. The external memory interface is

implemented with two controllers. The SRAM

controller allows the DSP to autoboot from a

parallel FLASH or EEPROM device. The SRAM

and SDRAM controllers are used to extend the data

memory of the DSP during runtime. A system can

use a FLASH/EEPROM device for autoboot, and

either SRAM or SDRAM for runtime memory. The

application user’s guide for a particular code load

will inform the system designer if memory is

required, and will specify the memory type and

speed. If no mention is made of external memory,

then external memory is not required for that

application. The SDRAM interface is not

available on the 100-pin device.

The signals for the external memory interface

are listed in Table 11.and Table 12.

For both controllers, memory access speed is

controlled by the DSP clock setting which is

constrained by the application code. The SRAM

interface is capable of in-system programming a

FLASH device. Wait states are available to support

slower FLASH/EEPROM and SRAM devices. The

SRAM interface supports 1Mx8 addressable space.

We recommend 12nS or better SRAM for optimal

performance. The SDRAM interface supports

16Mbit parts organized as 512k x 16bits x 2 banks

which yields a 1Mx16 addressable space. The burst

Pin Name

Pin Description

144-Pin

Number

100-Pin

Number

EXTA0

SRAM Address 0

EXTA1

SRAM Address 1

EXTA2

SRAM Address 2

EXTA3

SRAM Address 3

EXTA4

SRAM Address 4

EXTA5

SRAM Address 5

EXTA6

SRAM Address 6

EXTA7

SRAM Address 7

EXTA8

SRAM Address 8

EXTA9

SRAM Address 9

EXTA10

SRAM Address 10

EXTA11

SRAM Address 11

EXTA12

SRAM Address 12

EXTA13

SRAM Address 13

EXTA14

SRAM Address 14

EXTA15

SRAM Address 15

EXTA16

SRAM Address 16

EXTA17

SRAM Address 17

EXTA18

SRAM Address 18

EXTA19

SRAM Address 19

N/A

EXTD0

SRAM Data 0

EXTD1

SRAM Data 1

EXTD2

SRAM Data 2

EXTD3

SRAM Data 3

EXTD4

SRAM Data 4

EXTD5

SRAM Data 5

EXTD6

SRAM Data 6

EXTD7

SRAM Data 7

NV_OE#

SRAM Output Enable

NV_WE#

SRAM Write Enable

N/A

NV_CS#

SRAM Chip Select

Table 11. SRAM Interface Pins

Pin Name

Pin Description

144-Pin

Number

SD_DATA0

SDRAM Data 0

SD_DATA1

SDRAM Data 1

SD_DATA2

SDRAM Data 2

SD_DATA3

SDRAM Data 3

SD_DATA4

SDRAM Data 4

SD_DATA5

SDRAM Data 5

SD_DATA6

SDRAM Data 6

SD_DATA7

SDRAM Data 7

SD_DATA8

SDRAM Data 8

SD_DATA9

SDRAM Data 9

SD_DATA10

SDRAM Data 10

SD_DATA11

SDRAM Data 11

SD_DATA12

SDRAM Data 12

SD_DATA13

SDRAM Data 13

SD_DATA14

SDRAM Data 14

Table 12. SDRAM Interface Pins

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