CS494502 datasheet(14/100 Pages) CIRRUS

14 / 100 page

1.10 Switching Characteristics — Motorola® Host Slave Mode (DSPAB)

(TA =25 °C; VDD, PLLVDD = 2.5 V; VDDSD = 3.3 V; CL =20pF)

Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =

1/DCLK. The DSP clock can be defined as follows:

Internal Clock Mode:

DCLK ~ 60MHz before and during boot, i.e. DCLKP ~ 16.6ns

DCLK ~ 86 MHz after boot, i.e. DCLKP ~ 11.6ns

It should be noted that DCLK for the internal clock mode is application specific. The application code

users guide should be checked to confirm DCLK for the particular application.

Parameter

Symbol

Min

Max

Unit

Address setup before FCS and FDS low

Tmas

Address hold time after FCS and FDS low

Tmah

Read

Delay between FDS then FCS low or FCS then FDS low

Tmcdr

Data valid after FCS and FRD low with R/W high)

Tmdd

-21

FCS and FDS low for read

(Note 1)

Tmrpw

DCLKP + 10

Data hold time after FCS or FDS high after read

Tmdhr

Data high-Z after FCS or FDS high after read

Tmdis

-22

FCS or FDS high to FCS and FDS low for next read (Note 1)

Tmrd

2*DCLKP + 10

FCS or FDS high to FCS and FDS low for next write(Note 1)

Tmrdtw

2*DCLKP + 10

Write

Delay between FDS then FCS low or FCS then FDS low

Tmcdw

Data setup before FCS or FDS high

Tmdsu

FCS and FDS low for write

(Note 1)

Tmwpw

DCLKP + 10

R/W setup before FCS AND FDS low

Tmrwsu

R/W hold time after FCS or FDS high

Tmrwhld

Data hold after FCS or FDS high

Tmdhw

FCS or FDS high to FCS and FDS low with R/W high for

next read

(Note 1)

Tmwtrd

2*DCLKP + 10

FCS or FDS high to FCS and FDS low for next write(Note 1)

Tmwd

2*DCLKP + 10

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