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GMS81C7008 数据表(PDF) 76 Page - Hynix Semiconductor

部件名 GMS81C7008
功能描述  HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
PDF  123 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

GMS81C7008 数据表(HTML) 76 Page - Hynix Semiconductor

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GMS81C7008/7016
72
APR., 2001 Ver 2.01
18.2 Duty and Bias Selection of LCD driver
5 kinds of driving methods can be selected by DTY (bits 3 and 2
of LCD Control Register and connection of VCL pin externally.
Figure 18-3 shows typical driving waveforms for LCD.).
Figure 18-3 LCD drive waveform (Voltage COM-SEG Pins)
18.3 Selecting Frame Frequency
Frame frequency is set to the base frequency as shown in the fol-
lowing Table 18-1.
The LCK[1:0] of LCR determines the frequency of COM signal
scanning of each segment output. The watch timer must be en-
abled when the LCD display is turned on. RESET clears the LCD
control register LCR values to logic zero. The LCD display can
continue to operate even during the SLEEP and STOP modes if a
sub-frequency clock is oscillate and used as clock source of LCD
driver.
.
VCL2
VCL1
VCL0
GND
-VCL0
-VCL1
-VCL2
1/fF
Data “1”
(a) 1/4 duty, 1/3 bias
Data “0”
VCL2
VCL1
VCL0
GND
-VCL0
-VCL1
-VCL2
1/fF
Data “1”
(b) 1/3 duty, 1/3 bias
Data “0”
1/fF
Data “1” Data “0”
(c) 1/2 duty,1/3 bias
1/fF
Data “1”
Data “0”
VCL2
VCL1
VCL0
GND
-VCL0
-VCL1
-VCL2
(e) Static
Note: fF: LCD Frame Frequency
1/fF
Data “1” Data “0”
VCL2
GND
-VCL0 = -VCL1
-VCL2
(d) 1/2 duty, 1/2 bias
VCL1 = VCL0
VCL2
VCL1
VCL0
GND
-VCL0
-VCL1
-VCL2
LCK[1:0]
LCD clock
Frame Frequency (Hz)
(When fSUB = 32.768 kHz)
00
01
10
11
fSUB ÷ 32
fSUB ÷ 64
fSUB ÷ 128
fSUB ÷ 256
1024
512
256
128
Table 18-1 Setting of LCD Frame Frequency



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