GMS81C7008 datasheet(64/123 Pages) HYNIX

64 / 123 page

GMS81C7008/7016

APR., 2001 Ver 2.01

Serial I/O Mode Register(SIOM) controls serial I/O function.

The POL bit control which edge

According to SCK1 and SCK0, the internal clock or external

clock can be selected.

Serial I/O Data Register(SIOR) is an 8-bit shift register.

Figure 15-2 Block Diagram of SCI

15.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of

SIOM) to “1”. After one cycle of SCK, SIOST is cleared

automatically to “0”. The serial output data from 8-bit shift

is latched at rising edge of SCLK pin. When transmission

clock is counted 8 times, serial I/O counter is cleared as

‘0”. Transmission clock is halted in “H” state and serial I/

O interrupt(SIOIF) occurred.

Figure 15-3 SPI Timing Diagram at POL=0

R05/SCLK PIN

CONTROL CIRCUIT

R06/SOUT PIN

Serial IO Data

Octal Counter

Serial communication

Interrupt

SIOIF

R07/SIN PIN

SCK, SIO

overflow

SCK[1:0]

MUX

÷16

÷4

fXIN

fSXIN

SCMR[1:0]

T0OV

(Timer 0 overflow)

POL

SIOST

start

SIOSF

complete

clock

clear

SIO1

SIO0

[0FFH]

Edge Detector

SIO[1:0]

shift clock

SCLK OUT

SIOST

SCLK [R05]

(POL=0)

SOUT [R06]

SIN [R07]

SIOIF

(Interrupt Req.)

SIOSF

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