ICS5342 datasheet(12/36 Pages) ICST

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ICS5342

GENDAC

Microprocessor Interface

Below are listed the six microprocessor interface registers

within the ICS5342, and the register addresses through which

they can be accessed.

Asynchronous Access to Microprocessor Interface

Accesses to all registers may occur without reference to the

high speed timing of the pixel bit stream being processed by

the GENDAC. Data transfers between the color palette RAM

and the Color Value register, as well as modifications to the

Pixel Mask register, are synchronized to the Pixel Clock by

internal logic. This is done in the period between micropro-

cessor interface accesses. Thus, various minimum periods are

specified between microprocessor interface accesses to allow

the appropriate transfers or modifications to take place. Ac-

cess to PLL address, PLL parameter and to the command reg-

ister are asynchronous to the pixel clock.

The contents of the palette RAM can be accessed via the Col-

or Value register and the Pixel Address registers.

Writing to the color palette RAM

To set a new color definition, a value specifying a location in

the color palette RAM is first written to the Write mode Pixel

Address register. The values for the red, green and blue inten-

sities are then written in succession to the Color Value regis-

ter. After the blue data is written to the Color Value register,

the new color definition is transferred to the RAM, and the

Pixel Address register is automatically incremented.

Writing new color definitions to a set of consecutive locations

in the RAM is made easy by this auto-incrementing feature.

First, the start address of the set of locations is written to the

write mode Pixel Address register, followed by the color def-

inition of that location. Since the address is incremented after

each color definition is written, the color definition for the

next location can be written immediately. Thus, the color def-

initions for consecutive locations can be written sequentially

to the Color Value register without re-writing to the Pixel Ad-

dress register each time.

Reading from the RAM

To read a color definition, a value specifying the location in

the palette RAM to be read is written to the read mode Pixel

Address register. After this value has been written, the con-

tents of the location specified are copied to the Color Value

ments.

The red, green and blue intensity values can be read by a se-

quence of three reads from the Color Value register. After the

blue value has been read, the location in the RAM currently

specified by the Pixel Address register is copied to the Color

Value register and the Pixel Address again automatically in-

crements. A set of color values in consecutive locations can be

read simply by writing the start address of the set to the read

mode Pixel Address register and then sequentially reading the

color values for each location in the set. Whenever the Pixel

Address register is updated, any unfinished color definition

read or write is aborted and a new one may begin.

The Pixel Mask Register

The pixel address used to access the RAM through the pixel

interface is the result of the bitwise AND-ing of the incoming

pixel address and of the contents of the Pixel Mask register.

This pixel masking process can be used to alter the displayed

colors without altering the video memory or the RAM con-

tents. By partitioning the color definitions by one or more bits

in the pixel address, such effects as rapid animation, overlays,

and flashing objects can be produced.

The Pixel Mask register is independent of the Pixel Address

and Color Value registers.

The Command Register

The Command register is used to select the various GENDAC

color modes and to set the power down mode. On power up

this register defaults to an 8-bit Pseudo Color mode. This reg-

ister can be accessed by control pins RS2-RS0, or by a special

sequence of events for graphics subsystems that do not have

the control signal RS2. For graphic systems that do not have

RS2, this pin is tied low and an internal flag (HF: Hidden

Flag) is set when the pixel mask register is read four times

Memory Clock (CLK1) Default Frequency Register

MCLK

(MHz)

M & N

Code

Comments

45.00

4F 2B

Memory and GUI sub-

system clock

55.00

79 2E

Memory and GUI sub-

system clock

Microprocessor Interface Registers

RS2

RS1

RS0

Pixel Address (write mode)

Pixel Address (read mode)

Color Value

Pixel Mask

PLL Address (write mode)

PLL Parameter

Command

PLL Address (read mode)

0/HF

Command Register accessed by

(hidden) ﬂag after special

sequence of events.

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