ICS5342 datasheet(13/36 Pages) ICST

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ICS5342

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consecutively. Once the flag is set, the following Read or

Write to the pixel mask register is directed to the command

than the Pixel Mask register. The sequence has to be repeated

for any subsequent access to the command register.

The PLL Parameter Register

The CLK0 and CLK1 of the ICS5342 can be programmed for

different frequencies by writing different values to the PLL

parameter register bank. There are eight registers in the pa-

rameter register; seven are two bytes long and one (0E) is one

byte long.

Writing to the PLL parameter register

To write the PLL parameter data, the corresponding address

location is first written to the PLL address register. For soft-

ware compatibility with other chips, two address registers are

defined: the write mode PLL address register and the read

mode PLL address register. These are actually a single Read/

Write register in the ICS5342. The next PLL parameter write

will be directed to the first byte of the address location speci-

fied by the PLL address register. The next write to the param-

eter register will automatically be to the second byte of this

ically incremented. For the one byte “0E” register the address

location is incremented after the first byte write. If this fre-

quency is selected while programming, the output frequency

will change at the end of the second write.

Reading the PLL parameter register

To read one of the registers of the PLL parameter register the

address value corresponding to the location is first written to

the PLL address register. The next PLL parameter read will be

directed to the first byte of the address location pointed by this

index register. A next read of the parameter register will auto-

matically be the second byte of this register. At the end of the

second read, the address location is automatically increment-

ed. The address register (0E) is incremented after the first byte

read.

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