ICS5342 datasheet(3/36 Pages) ICST

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ICS5342

GENDAC

CLK1

Output

Memory clock output – used to time video memory

CLK0

Output

Video clock output – provides a CMOS level pixel or dot clock frequency to

graphics controller – output frequency is determined by values of PLL registers

CS0

Input

Clock select 0 – The status of CS0-1 determines which frequency is selected on

the CLK0 (video) output.

CS1

Input

Clock select 1– status of CS0-1 determines which frequency is selected on CLK0

(video) output

VREF

I/O

Internal reference voltage – normally connects to a 0.1

µf capacitor to ground – to

use external Vref, connect 1.235V reference to this pin

RSET

Input

Resistor set – pin used to set current level in analog outputs – usually connected

through 1/4W, 1% resistor to ground

SENSE*

Output

Monitor sense – Pin is active low when any of red, green, or blue outputs >385mV.

Sense output is high when all analog outputs are < 275 mV. Chip has on-board

comparators and internal 1.235 V voltage reference. This signal is used to detect

monitor type.

BLUE

GREEN

RED

Output

Color signals from DAC analog outputs – Each DAC comprises several current

sources of which outputs are added together according to the applied binary value.

The outputs are typically used to drive a CRT monitor.

P15- P0

13,12,4,1

67-64,

58-51

Input

Pixel address lines – Byte-wide information is latched by the rising edge of PCLK

when using the color palette, and is masked by the Pixel Mask register. Values are

used to specify the RAM word address in default mode (accessing RAM). In Hi-

Color XGA, and True Color modes, they represent color data for the DACs.

Ground inputs if they are not used.

PCLK

Input

Pixel Clock – rising edge of PCLK controls latching of the Pixel Address and

BLANK* inputs – clock also controls progress of these values through the three-

stage pipeline of the Color Palette RAM, DAC, and outputs

STROBE*

Input

latches input clock select signals CS0-CS1

BLANK*

Input

Composite BLANK* Signal, active low. When BLANK* is asserted, outputs of

DACs are zero which blacks screen. DACs are automatically powered down to

save current during blanking. Color palette may still be updated through D0-D7

during blanking.

CVDD

CLK1 Power Supply – connect to DVDD

CVDD

CLK0 power supply – connect to AVDD

AVDD

DAC power supply – Connect to AVDD

DVDD

Digital power supply

XVDD

Crystal oscillator power supply– connect to AVDD

CVDD

CLK power supply – connect to DVDD

CGND

VSS for CLK1 – connect to ground.

CGND

VSS for CLK0 – connect to ground

XGND

VSS for crystal oscillator

AGND

DAC ground – connect to ground

DGND

Digital ground – connect to ground

CGND

VSS for CLK – connect to ground

N/C

28-35,

39,45,

Not connected – leave ﬂoating or tie to ground

Pin Description (68-pin PLCC)

Symbol

Pin #

Type

Description

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