ICS5342 datasheet(18/36 Pages) ICST

18 / 36 page

ICS5342

GENDAC

N2 Post Divide Code

If mode 4 is set in the command register, CR7-CR4 bits equal

0001, and the N2 code must be 10.

The block diagram of the PLL clock synthesizer is shown in

figure 3.

Based on the M and N values, the output frequency of the

clocks is given by the following equation:

M and N values should be programmed such that the frequen-

cy of the VC0 is within the optimum range for duty cycle, jit-

ter and glitch free transition. Optimum duty cycle is achieved

by programming N2 for values greater than unity. See the next

section for a programming example.

Programming Example

Suppose an output frequency of 25.175 MHz is desired. The

reference crystal is 14.318 MHz. The VCO should be targeted

to run in the 60 to 270 MHz range, so choosing a post divide

of 4 gives a VCO frequency of:

From the table in the previous section, we find N2 = 2 Substi-

tuting FREF = 14.318 and 2

N2 = 4 into the clock frequency

equation in the previous section:

By trial and error:

M + 2 = 127

M = 125

N1 + 2 = 18

N1 = 16

so the registers are:

M = 125d = 1 1 1 1 1 0 1 b

N = 0 & N2 code & N1 = 0 & 1 0 & 1 0 0 0 0

N = 0 1 0 1 0 0 0 0 b

Additional Information on Programming

the Frequency Generator section of the

GENDAC

When programming the GENDAC PLL parameter registers,

there are many possible combinations of parameters which

will give the correct output frequency. Some combinations are

better than others, however. Here is a method to determine

how the registers need to be set:

The key guidelines come from the operation of the phase

locked loop, which has the following restrictions:

This refers to the input refer-

ence frequency. Most users simply connect a 14.318

MHz crystal to the crystal inputs, so this is not a prob-

lem.

This is the frequency input to

the phase detector.

This is the VCO

frequency. In general, the VCO should run as fast as pos-

sible, because it has lower jitter at higher frequencies.

Also, running the VCO at multiples of the desired fre-

quency allows the use of output divides, which tends to

improve the duty cycle.

This is the output fre-

quency.

These rules lead to the following procedure for determining

the PLL parameters, assuming rules 1 and 4 are satisfied.

A. Determine the value of N2 (either 1, 2, 4 or 8) by select-

ing the highest value of N2, which satisﬁes the condition

N2* fCLK < 270 Mhz.

B. Calculate:

C. Now (M+2) and (N1+2) must be found by trial and error.

With a 14.318 MHz reference frequency, there will gen-

erally be a small output frequency error due to the reso-

lution limit of (M+2) and (N1+2). For a given frequency

tolerance, several different (M+2) and (N1+2) combina-

tions can usually be found. Usually, a few minutes trying

N2 Post Divide Code

N2 Code

Divider

OUT

()F

REF

2N2 N12

()

---------------------------------

25.175

101.021 MHz

25.175

14.318

---------------- 4

〈〉

N12

-----------------

2 MHz

REF

25 MHz

600KHz

REF

N12

-----------------

8MHz

≤≤

60MHz

N12

----------------- f

REF

〈〉 270 MHz

≤≤

CLK 0 and f CLK 1

35 MHz

≤

N 12

-----------------

2N2 f

OUT

REF

-----------------------

ICS5342 数据表(PDF) 18 Page - Integrated Circuit Systems

ICS5342 数据表(HTML) 18 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表下载

链接网址

ICS5342 数据表(PDF) 18 Page - Integrated Circuit Systems

ICS5342 数据表(HTML) 18 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

数据表 下载

链接网址

数据表下载