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AD1953 数据表(PDF) 7 Page - Analog Devices

部件名 AD1953
功能描述  SigmaDSP 3-Channel, 26-Bit Signal Processing DAC
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD1953 数据表(HTML) 7 Page - Analog Devices

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AD1953
–7–
PIN FUNCTION DESCRIPTIONS
Input/
Pin No.
Mnemonic
Output
Description
1
NC
No Connect
2
MCLK2
IN
Master Clock Input 2 256/512 fS
3
MCLK1
IN
Master Clock Input 1 256/512 fS
4
MCLK0
IN
Master Clock Input 0 256/512 fS
5
AUXDATA
IN
Auxiliary Serial Data Input
6
MUTE
IN
Mute Signal, Initiates Volume Ramp-Down
7
DVDD
Digital Supply for DSP Core, 4.5 V to 5.5 V
8
SDATA2
IN
Serial Data Input 2
9
BCLK2
IN
Bit Clock 2
10
LRCLK2
IN
Left/Right Clock 2
11
SDATA1
IN
Serial Data Input 1
12
BCLK1
IN
Bit Clock 1
13
DGND
Digital Ground
14
LRCLK1
IN
Left/Right Clock 1
15
SDATA0
IN
Serial Data Input 0
16
BCLK0
IN
Bit Clock 0
17
LRCLK0
IN
Left/Right Clock 0
18
CDATA
IN
SPI Data Input
19
CCLK
IN
SPI Data Bit Clock
20
CLATCH
IN
SPI Data Framing Signal
21
RESETB
IN
Reset Signal, Active Low
22
AVDD
Analog 5 V Supply
23
AGND
Analog GND
24
NC
No Connect
25
VOUTS–
OUT
Negative Sub Analog DAC Output
26
VOUTS+
OUT
Positive Sub Analog DAC Output
27
AGND
Analog GND
28
VOUTR–
OUT
Negative Left Analog DAC Output
29
VOUTR+
OUT
Positive Left Analog DAC Output
30
AVDD
Analog 5 V Supply
31
AGND
Analog GND
32
AVDD
Analog 5 V Supply
33
VOUTL+
OUT
Positive Left Analog DAC Output
34
VOUTL–
OUT
Negative Left Analog DAC Output
35
AGND
Analog GND
36
NC
No Connect
37
NC
No Connect
38
VREF
IN
Connection for Filtered AVDD/2
39
FILTCAP
IN
Connection for Noise Reduction Capacitor
40
ZEROFLAG
OUT
Zero Flag Output. High when both left and right channels are 0 for 1024 frames.
41
DMUXO/TDMO
OUT
Dual-function Pin: Serial Data MUX Output/TDM Mode Output Data
42
BMUXO/TDMBC
OUT
Dual-function Pin: Bit Clock MUX Output/TDM Mode Bit Clock Output (256 fS)
43
LRMUXO/TDMFS
OUT
Dual-function Pin: Left/Right Clock MUX Output/TDM Mode Frame Sync
Clock Output
44
ODVDD
Digital Supply Pin for Output Drivers, 2.5 V to 5.5 V
45
DCSOUT
OUT
Data Capture Serial Output for Data Capture Registers. Use in conjunction
with selected LRCLK and BCLK to form a 3-wire output.
46
COUT
OUT
SPI Data Output, Three-Stated when Inactive
47
MCLKOUT
OUT
Master Clock Output 512/256 fS (Frequency Selected by SPI Register)
48
DGND
Digital Ground



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