AD1953_15 datasheet(21/36 Pages) AD

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AD1953

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Control Register 1

Control Register 1 is a 14-bit register that controls data capture

modes, serial modes, de-emphasis, mute, power-down, and

SPI-to-memory transfers. Table III documents the contents of

this register. Table IV details the two bits in the register’s

read operation.

Bits <1:0> set the wordlength, which is used in right-justified

serial modes to determine where the MSB is located relative to

the start of the audio frame.

Bits <3:2> select one of four serial modes, which are discussed

in the Serial Data Input Port section.

The de-emphasis curve selection Bits <5:4> turn on the internal

de-emphasis filter for one of three possible sample rates.

Bit <6>, the soft power-down bit, stops the internal clocks to

the DSP core, but does not reset the part. The digital power

consumption is reduced to a low level when this bit is asserted.

Reset can only be asserted using the external reset pin.

Soft mute (Bit <7>) is used to initiate a volume ramp-down

sequence. If the initial volume was set to 1.0, this operation will

take 512 audio frames to complete. When this bit is deasserted,

a ramp-up sequence is initiated until the volume returns to its

original setting.

The initiate-safe-transfer Bit <9> will request a data transfer

from the SPI safeload registers to the parameter RAM. The

safeload registers contain address-data pairs, and only those

registers that have been written to since the last transfer opera-

tion will be uploaded. The user may poll for this operation being

complete by reading Bit <0> of Control Register 1. The Safeload

Mechanism section goes into more detail on this feature.

Bit <10>, the halt program bit, is used to initiate a volume

ramp-down followed by a shutdown of the DSP core. The user

may poll for this operation being complete by reading Bit <1>

of Control Register 1.

The Data Capture Serial Out mode is controlled with Bits

<13:12>. This function can be used to send data that is cap-

tured using the data-capture feature to external devices such as

an external stereo DAC or multichannel codec. The Data Cap-

ture Registers and Outputs section gives more information about

the TDM and data capture features.

Table III. Control Register 1 Write Definition

Function

13:12

Data Capture Serial Out Mode Control

00 = none

01 = TDM 6-channel out, uses Pins 41–43

10 = 2-channel out, uses Pin 45

11 = Unused

Unused

Halt Program (1 = Halt)

Initiate Safe Transfer (1 = Transfer)

Unused

Soft Mute (1 = Start Mute Sequence)

Soft Power-Down (1 = Power Down)

5:4

De-emphasis Curve Select

00 = none

01 = 44.1 kHz

10 = 32 kHz

11 = 48 kHz

3:2

Serial In Mode

00 = I

01 = Right-Justified

10 = DSP

11 = Left-Justified

1:0

Word Length

00 = 24 Bits

01 = 20 Bits

10 = 16 Bits

11 = 16 Bits

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